Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-22
2001-09-11
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290
Reexamination Certificate
active
06288940
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device allowing the presence of inoperative memory cells.
2. Description of the Related Art
In recent years, cellular phones have accomplished not only a vocal communication but also the transmittance of character or image data. The information content of cellular phone has increased and the capacity of a memory device built in the cellular phones tends to enlarge. In addition, a delivering service for music data has started on the Internet. The delivered music data are stored in a portable storage device, and are played back by, for example, inserting the storage device into a portable audio equipment.
As the portable equipment has spread described above, a large number of memory devices mounted or set on the portable equipment have been demanded. The memory device of this type needs to be low in power consumption (especially in a standby state), large in storage capacity and small in size. Further, the memory device of this type is often subjected to file management in which one block or sector is composed of a plurality of bits. In this case, some of the bits are allowed to be defective in the memory device as in a hard disk or a floppy disk.
A flash memory is non-volatile and capable of having electrically data written and erased data so it is the most suitable for the portable equipment. Therefore, the production of flash memories has yearly increased. In general, the memory cell array of the flash memory is constructed of a plurality of blocks (sometimes called sectors). The block is the minimum unit of erasing data stored in memory cells. Besides, the block is constituted of a plurality of pages.
FIG. 1
shows the flow of the full chip erase of data written in the flash memory.
First, at a step S
201
, a counter value indicating a block number is set at zero.
Subsequently, at a step S
202
, it is checked if the data of a block indicated by the counter value have been erased. In a case where the data have been erased, the procedure shifts to a step S
204
. In a case where the data have not been erased, the procedure shifts to a step S
203
.
At the step S
203
, all the blocks of the flash memory are selected and the data erase operation thereof is performed. Thereafter, the procedure shifts to the step S
202
again.
At the step S
204
, it is checked if the block number indicated by the counter value is the maximum. In a case where the block number is the maximum, the batch erasing operation of the data is completed. In a case where the block number is not the maximum, the procedure shifts to a step S
205
.
At the step S
205
, the counter value is incremented by one, thereby increasing the block number indicated by the counter. Thereafter, the procedure shifts to the step S
202
.
Then, the procedure is repeated until the whole chip is fully erased.
Conventionally, the flash memory was shipped with the operations of all the implemented blocks guaranteed. However, in the case where the flash memory is used for file similar to hard disks or floppy disks as described above, all the blocks need not always be good. Therefore, the flash memory allowing a predetermined number of blocks to be bad (hereinafter referred to as “flash memory for file use”) has been shipped. In general, the flash memory for file use has been developed in an NAND type or an AND type which has advantage for a high density.
Meanwhile, memory cells within the bad block cannot have the data of all their bits erased with reliability. With the flash memory for file use, therefore, the procedure always shifts to the step S
203
after processing of the step S
202
when performing the full chip erase of the data as shown in FIG.
1
. In other words, the flash memory for file use has the problem that the full chip erase operation is never completed.
Furthermore, users who purchase the flash memory for file use need to manage the presence of the bad blocks in the flash memory by creating a table or the like.
FIG. 2
shows a flow for creating a bad block table. The flow is executed by a system mounting the flash memory, or the inspection apparatus of the users. The flash memory is shipped with all the bits of its good blocks erased.
First, at a step S
101
, the value of a counter indicating a block number is set at zero.
Subsequently, at a step S
102
, it is checked if the data of those “0” and “1” of pages within a block indicated by the counter value have been erased. In a case where all the data of the pages “0” and “1” have been erased, the block is judged to be good, and the procedure shifts to a step S
104
. In a case where the data of the pages “0” and “1” have not been erased, the block is judged to be bad, and the procedure shifts to a step S
103
. Incidentally, at the step S
102
, the data erasure may well be checked for all the pages within the block.
At the step S
103
, the counter value is stored as a bad block number in the bad block table, and the procedure shifts to the step S
104
.
At the step S
104
, it is checked if the block number indicated by the counter value is the maximum. In a case where the block number is the maximum, the creation of the bad block table is completed. In a case where the block number is not the maximum, the procedure shifts to a step S
105
.
At the step S
105
, the counter value is incremented by one, thereby to increase the block number indicated by the counter. Thereafter, the procedure shifts to the step S
102
.
Then, the above procedure is repeated until the bad block table is created. The bad block table must be made for every purchased flash memory, causing large workload thereof.
Furthermore, the system mounting the flash memory needs to be controlled according to the bad block table in order to access any bad block.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a non-volatile semiconductor memory device capable of controlling bad blocks by itself.
Another object of the present invention is to easily perform a data erase operation in a non-volatile semiconductor memory device allowing the presence of bad blocks.
According to one of the aspects of a non-volatile semiconductor memory device in the present invention, the device comprises a plurality of memory cell units, each including a plurality of non-volatile memory cells capable of having electrically data rewritten; a storage unit; and an access inhibiting circuit. The storage unit stores defect information of the memory cell unit not normally operating. The access inhibiting circuit judges the condition of the memory cell unit within the device according to the defect information stored in the storage unit. Access to the memory cell unit not normally operating is inhibited in accordance with the resultant. Users of the device need not manage the defective memory cell unit since the device itself can control the information of the memory cell unit not normally operating. This improves the usability of the device and reduces the cost of a system mounting the device.
According to another aspect of the non-volatile semiconductor memory device in the present invention, the storage unit is formed of non-volatile elements. Therefore, the defect information of the memory cell unit not normally operating is held in the device independent of the switch-on/off of the power supply. For example, after the probing test of the device on a wafer or the classification test of the package thereof, the defect information can be stored in the storage unit by utilizing the test results. In other words, the defect information is stored in the storage unit before the shipment of the device. This makes it unnecessary for users of the device to create a bad block table or the like, resulting in greatly improving the usability.
According to another aspect of the non-volatile semiconductor memory device in the present invention, the storage unit is constructed of non-volatile memory cells respectively formed in the memory
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nguyen Tan T.
LandOfFree
Non-volatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2499036