Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-05-24
2001-03-20
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C438S734000, C438S740000, C438S745000
Reexamination Certificate
active
06204185
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a borderless contact process, and more particularly, to a semiconductor device including a self-align stop layer for borderless contact process within shallow trench isolation. The provided semiconductor device can be simplified and result in fine borderless contact fabrication.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of integrated circuits (ICs). More particularly, as more than hundreds or thousands of electrical components are integrated into the ICs, a means for improving quality and reducing critical dimension of semiconductor devices has become imperative. Accordingly, with misalignment tolerance for the borderless contact formation, so silicon nitride layer must be used as a stop layer of borderless contact etching to avoid the oxide recess which will induce junction leakage currents.
In the sub-micro dimension, a borderless contact process is used to save the layout area. This usually needs a stop layer cap (for example, silicon nitride layer
300
) in inter-layer dielectric (ILD)
320
layer to prevent junction from damage for shallow trench isolation (STI)
200
process during the contact etch step. In the contact etching step, first, oxide was etched and stooped on silicon nitride layer
300
, and then the silicon nitride cap layer was etched and prevented from over-etching (e.g., oxide loss was controlled at the shallow trench isolation) to attack junction. This stop layer makes contact etching scheme complicated.
FIGS. 1A
to
1
D show cross-sectional views of a traditional semiconductor device, where the structure shown in
FIG. 1D
has additional gate oxide
120
and polysilicon layer
220
. An N-type semiconductor device, for example, has a source/drain region
280
B and
280
C doped with N-type ions, which are usually designated as N
+
regions. The substrate
100
usually has a P-type well, and the gate
220
is composed of polysilicon, and the spacers
260
.
For submicron technology, the shallow trench isolation (STI) was employed for global planarization process. However, an oxide recess (especially as the corner of STI) will happen during the post-wet-dip treatment in STI process, and thus subthreshold kink effect will happen.
On the other hand, small contact was necessary to meet the requirement of the design rule, and thus the borderless contact was used to increase the critical dimension of contact size and process margin for small contact formation.
SUMMARY OF THE INVENTION
In accordance with the present invention, a semiconductor device is provided for achieving a larger process margin. Primarily, the purpose of the present invention provides means for manufacturing a semiconductor device with silicon nitride layer within shallow trench isolation as a self-align stop layer for borderless contact process, so that the provided semiconductor device can be adapted to achieve more simplified fabrication.
Another purpose of the present invention is to provide a semiconductor device with a self-aligned stop layer composed of silicon nitride within shallow trench isolation (STI). Therefore, borderless contact etching process only needs to etch oxide layer and no need to breakthrough stop layer on diffusion. Borderless contact etching can be stopped on the silicon nitride layer within shallow trench isolation to avoid junction leakage.
In one embodiment, the present invention provides a semiconductor device that can simplify borderless contact fabrication, which includes a self-align stop layer for borderless contact process within shallow trench isolation. Next, a pad oxide, a pad polysilicon, and a first silicon nitride layer are formed in order over the substrate. A first photoresist layer is formed over the first silicon nitride layer. Consequentially, the first silicon nitride layer, the pad polysilicon, said the pad oxide, and the substrate are etched using the photoresist layer as a mask to form shallow trench isolation inside the silicon substrate. A first silicon dioxide layer is deposited over the device and shallow trench isolation inside the silicon substrate. Then, the first silicon dioxide layer is removed by using first silicon nitride layer as a stop layer, wherein the surface of the first silicon dioxide layer within STI is lower than top surface of the silicon substrate by a chemical mechanical polishing (CMP) and etching back. Next, a second silicon nitride layer is deposited over the wafer and the shallow trench isolation inside the silicon substrate, and used second silicon nitride layer as a stop layer of a borderless contact. Wherein the first silicon nitride layer and a portion of the pad polysilicon layer are removed by a CMP process which used pad polysilicon layer as a stop layer. Hence, the remaining pad polysilicon layer and the pad oxide layer are removed until a portion of the surface of the silicon substrate is exposed. A gate oxide is formed over the silicon substrate, thus forming a polysilicon layer on the gate oxide layer. Then, the polysilicon layer is etched to form a gate. Consequentially, first ions of a first conductive type are implanted into the silicon substrate. And forming a third silicon nitride spacer on sidewall of the gate. Second ions of the first conductive type are implanted into the silicon substrate to form source/drain regions using the spacer as a mask, wherein concentration of the implanted second ions is greater than concentration of the implanted first ions. Finally, an inter-layer dielectric is deposited over the silicon substrate, followed by a planarization process such as chemical mechanical polishing (CMP), wherein the inter-layer dielectric is etched to form a borderless contact therein between the isolation and source/drain regions.
REFERENCES:
patent: 5759867 (1998-06-01), Armacost et al.
patent: 5935875 (1999-08-01), Lee
Powell William
United Microelectronics Corp.
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