Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-01-04
2001-07-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06261923
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming planarized shallow trench isolation (STI) in the fabrication of integrated circuits.
2. Description of the Prior Art
As device technology is scaled down to the quarter micron regime, the use of the conventional local oxidation of silicon (LOCOS) isolation will be confined by smaller channel-width encroachment (bird's beak). Shallow trench isolation (STI) can be used to eliminate these encroachments, especially in ultra large scale integrated (ULSI) circuit devices. To achieve good planarity after STI, chemical mechanical polishing (CMP) is often used. However, due to pad deformation, the trench open area is susceptible to dishing which causes oxide thinning in the wide trench.
A number of workers in the art have addressed the CMP planarization issue. U.S. Pat. No. 4,962,064 to Haskell et al and the prior art of U.S. Pat. No. 5,721,173 to Yano et al teach the use of a polysilicon hard mask layer in planarizing shallow trench isolation (STI). U.S. Pat. No. 5,356,513 to Burke et al uses a series of alternating “hard” and “soft” polishing layers for planarizing an oxide layer over a metal pattern. U.S. Pat. No. 5,290,396 to Schoenborn et al and U.S. Pat. No. 5,441,094 to Pasch disclose a silicon nitride hard mask and a one-step CMP process. U.S. Pat. No. 5,575,886 to Murase shows a global planarization process using CMP.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the invention is to provide a process for forming planarized isolation in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming planarized isolation in which oxide dishing is eliminated.
Still another object is to provide a process for forming planarized isolation using a nitride mask and two CMP steps.
In accordance with the objects of the invention, a method for forming planarized isolation using a nitride hard mask and two CMP steps is achieved. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer and pad oxide layer are etched through where they are not covered by a mask to provide openings where the surface of the semiconductor substrate is exposed wherein there is at least one wide opening and at least one narrow opening. A trench is etched into the semiconductor substrate where it is exposed within the wide and the narrow openings. An oxide layer is deposited overlying the first nitride layer and within the trenches wherein the narrow trench is completely filled and a trough is formed over the wide trench. A second nitride layer is deposited over the oxide layer. The second nitride layer is polished away with a polish stop at the oxide layer whereby the second nitride layer is removed except where it lies within the trough. The oxide layer is etched back where it is not covered by the second nitride layer wherein the oxide layer is planarized except where the oxide layer underlies the second nitride layer. The second nitride layer is removed within the trough whereby oxide horns forming the trough extend vertically upward from the planarized oxide surface. Thereafter, the oxide layer is polished away with a polish stop at the first nitride layer whereby the oxide horns are removed. The first nitride layer and the pad oxide layer are removed completing formation of the shallow trench isolation in the fabrication of an integrated circuit device.
REFERENCES:
patent: 4962064 (1990-10-01), Haskell et al.
patent: 5290396 (1994-03-01), Schoenborn et al.
patent: 5356513 (1994-10-01), Burke et al.
patent: 5441094 (1995-08-01), Pasch
patent: 5575886 (1996-11-01), Murase
patent: 5710076 (1998-01-01), Dai et al.
patent: 5721172 (1998-02-01), Jang et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5817567 (1998-10-01), Jang et al.
patent: 5960306 (1999-09-01), Hall et al.
patent: 6027959 (2000-02-01), En et al.
Kuo Ming-Hong
Lin Wei-Ray
Yang Fu-Liang
Ackerman Stephen B.
Chaudhuri Olik
Duy Mai Anh
Pike Rosemary L. S.
Saile George O.
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