Method and system for a RISC graphics pipeline optimized for...

Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors

Reexamination Certificate

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C345S426000, C345S440000

Reexamination Certificate

active

06236413

ABSTRACT:

FIELD OF THE INVENTION
The field of the present invention pertains to computer implemented graphics. More particularly, the present invention relates to a system and method for implementing complex operations in a streamlined high speed graphics pipeline of a computer graphics system.
BACKGROUND OF THE INVENTION
Computer graphics are being used today to perform a wide variety of tasks. Many different areas of business, industry, government, education, entertainment, and most recently, the home, are tapping into the enormous and rapidly growing list of applications developed for today's increasingly powerful computer devices.
Graphics have also become a key technology for communicating ideas, data, and trends in most areas of commerce, science, and education. Until recently, real time user interaction with three dimensional (3D) models and pseudo-realistic images was feasible on only very high performance workstations. These workstations contain dedicated, special purpose graphics hardware. The progress of semiconductor fabrication technology has made it possible to do real time 3D animation, with color shaded images of complex objects, described by thousands of polygons, on powerful dedicated rendering subsystems. The most recent and most powerful workstations are capable of rendering completely life-like, realistically lighted, 3D objects and structures.
In a typical 3D computer generated object, the surfaces of the 3D object are described by data models. These data models store “primitives” (usually mathematically described polygons and polyhedra) that define the shape of the object, the object attributes, and the connectivity and positioning data describing how the objects fit together. The component polygons and polyhedra connect at common edges defined in terms of common vertices and enclosed volumes. The polygons are textured, Z-buffered, and shaded onto an array of pixels, creating a realistic 3D image.
In a typical graphics computer, most of the actual rendering computation is performed by a graphics subsystem included in the graphics computer. The 3D object data models are “traversed” by a software program (e.g., in response to user input) running on one or more processors in a processor subsystem within the graphics computer. The primitives describing the 3D object are processed by the processor subsystem and sent to the graphics subsystem for rendering. For example, a 3D polyhedra model of an object is sent to the graphics subsystem as contiguous strips of polygons, sent to the graphics subsystem as a graphics data stream (e.g., primitives, rendering commands, instructions, etc.). This graphics data stream, sometimes referred to as a command data stream, provides the graphics subsystem with all the information required to render the 3D object and the resulting scene. Such information includes, for example, specular highlighting, anti-aliasing, depth, transparency, and the like. Using this information, the graphics subsystem performs all the computational processing required to realistically render the 3D object. The hardware of the graphics subsystem is specially tuned to perform such processing quickly and efficiently in comparison to the processor subsystem.
To facilitate fast and efficient graphics processing, typical graphics subsystems are deeply pipelined. This refers to the architecture of the graphics subsystem wherein the graphics processing hardware includes many different stages for processing graphics data and commands. The large number of stages are sequenced and linked such that at any given instant, several data items or commands are being processed. Each stage is optimized to perform specific task. When it completes its task, another graphics command or data item is ready for processing. In this manner, commands and data proceed down the stages of the pipeline in “assembly line” fashion, at much faster speeds than possible with non-pipelined processing hardware. A modern, deeply pipelined, graphics processing subsystem can run at clock speeds of 266 MHz or more, processing enormous amounts of data.
However, even these speeds are not sufficient for the most demanding 3D applications currently being envisioned. Such applications require the traversal of very large data models and the generation, display, and interaction with highly complex 3D objects, often in real-time. A partial list of such applications include the generation of special effects for movies, real-time engineering design simulations, weather prediction, high fidelity virtual reality, computational fluid dynamics, medical diagnostic imaging, etc. The need for traversing very large data models and processing the resulting graphics data requires that vast amounts of data be processed at extremely fast speeds.
Thus, what is required is a method and system which effectively provides for greatly increased graphics subsystem bandwidth. What is required is a method and system which accommodates the enormous bandwidth requirements of the most demanding 3D visualization applications. What is further desired is a method of servicing the bandwidth requirements of the above applications efficiently, without a large amount of redundant logic, while retaining the ability to perform complex graphics operations. The required system should leverage existing processing hardware of 3D graphics subsystems to improve cost effectiveness. The method and system of the present invention provides a novel solution to the above requirements.
SUMMARY OF THE INVENTION
The present invention is a method and system which effectively provides for greatly increased graphics subsystem bandwidth. The present invention provides a system which accommodates the enormous bandwidth requirements of the most demanding 3D visualization applications. In addition, the present invention provides a method and system for servicing the bandwidth requirements of the above applications efficiently, without a large amount of redundant logic and its attendant expense. The system of the present invention leverages existing processing hardware of 3D graphics subsystems to improve cost effectiveness.
In one embodiment, the present invention comprises a reduced instruction set graphics processing subsystem in a graphics computer system. The instruction set is reduced in that the hardware of the graphics processing subsystem is optimized to execute a subset of the available graphics instructions (e.g., OpenGL v1.1) in a very efficient, streamlined manner. Instructions from this subset execute in a single pass through the multistage pipeline of the graphics subsystem. These instructions are the more simple, more frequently used instructions.
In accordance with the present invention, The more complex instructions are not “directly” implemented in hardware in a single pass. These instructions are implemented by passing the operation through the pipeline multiple times, accomplishing multiple passes. With each pass, the intermediate results are processed, until the complex instruction is completed.
Multi-pass processing is implemented through the use of recirculation pipes built into the components of the graphics processing subsystem. For example, in the case of a texture-shader subsystem, the subsystem's internal components, such as the texture filter unit, the texture environment unit, the per-pixel lighting unit, the light environment unit, and the like, each have a respective recirculation pipe. The recirculation pipes enable the intermediate results of complex operations to be fed back for additional processing. The same recirculation pipes are used to handle pipeline stalls due to, for example, cache faults in the texture-shader subsystem's coupled cache.
Since the hardware does not have to directly support complex operations, the hardware can be streamlined and optimized to execute the simple operations at maximum speed, thus, making the graphic pipeline hardware very efficient. This enables the fast execution of complex instructions, even though they require multiple passes. In this manner, the present invention services the

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