Pulse or digital communications – Synchronizers – Self-synchronizing signal
Reexamination Certificate
1999-03-19
2001-08-21
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Self-synchronizing signal
C375S348000
Reexamination Certificate
active
06278754
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a demodulator for use in an asynchronous satellite communications system. More specifically, the present invention relates to a demodulator circuit and method for detection and transition sample estimation in a shared multi-carrier environment.
DESCRIPTION OF RELATED ART
Traditionally, satellites have performed the function of a simple repeater in the sky. More is recently, new satellite architectures have been proposed that require on-board demultiplexing and demodulation of frequency-division multiple access (FDMA) up-link carriers, baseband processing, routing, remultiplexing, and remodulation for down-link transmissions. This on-board baseband signal regeneration provides significant connectivity and link advantages.
For asynchronous networks, the various carrier up-link transmissions are not clock-synchronous. When using a block demultiplexer architecture, the samples at the demultiplexer output are timed relative to the clock that controls the demultiplexer. Therefore, it is not possible to synchronize the demultiplexer output samples with the symbols of the various carriers. On the other hand, the number of samples used in the demodulator is ordinarily established by the need to sample the carrier signal appearing at the demodulator input at a rate that is a precise integer multiple of (e.g. usually twice) the symbol rate. Furthermore, the time phase of these samples must be adjusted to align the samples at the proper positions in each symbol. To bridge this gap between the demultiplexer output and the demodulator input, a sample interpolator has been typically used. However, the conventional interpolator function is computationally intensive, thus requiring a substantial amount of power.
An improvement was described in a paper published in
1990
by Soheil Sayegh entitled “DSM MCD for FUTURE IBS/IDR Services”, Second International Workshop on Digital Signal Processing Techniques Applied to Space Communications. This paper, incorporated herein by reference, describes the concept of a multi-carrier demodulator (MCD) capable of handling asynchronous input samples and not requiring a synchronous network. At the same time, the MCD is reprogrammable from the ground to handle different frequency plans and carrier data rates. To accomplish the handling of asynchronous input samples, the MCD incorporates a digital signal processing scheme called Detection/Transition Sample Estimation (DTSE) for demodulating asynchronous samples in a multi-rate environment.
DTSE utilizes the value and position of the two samples that bound the mid-symbol point to estimate the value of the detection sample, while the transition (end-of-symbol) sample is estimated in a similar manner. In the data detection path, an additional stage of inter-symbol interference removal processing can be added to improve the value of the detection sample before symbol resolution.
The above-cited paper contemplates the use of a high precision counter to keep track of relative sample position within a symbol, and then simply classifying each sample as L (left), R (right) or &zgr; (unused) depending on the position within a symbol. It is a requirement for proper operation of a DTSE system that the first used sample be a left (L) sample and that the sample immediately following be a right (R) sample. However, due to timing corrections which may be made between samples, it is possible for the samples to be classified such that this requirement is not satisfied, e.g., with two successive samples being classified as L or R, an L sample followed by an unused sample, etc., resulting in faulty operation.
A further problem with prior art in digital processing in general is that, in operation with multiple channels, there may be a significant time penalty in storing the register contents for one channel and retrieving from memory the information to be loaded into registers for continued processing of the next channel.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a demodulator circuit which operates with low power dissipation, and which is not subject to the sample position ambiguity of the prior art.
It is a further object of the present invention to provide a demodulator circuit which can more efficiently operate with multiple channels.
The demodulator circuit according to the present invention includes an initial detection sample estimation circuit which receives the input data signal, takes a plurality of samples for each symbol of the input data signal and produces an estimated detection sample of the input data signal based on the plurality of samples, which may optionally be delivered to an inter-symbol interference (ISI) removal circuit. Also included in the demodulator circuit is a transition sample estimation circuit which receives the input data signal, takes a plurality of samples for each symbol of the input data signal and produces an estimated transition sample based on the plurality of samples.
The demodulator circuit also includes a clock loop error detection and loop filter circuit which receives the estimated transition sample and produces an estimated symbol timing correction value. The demodulator circuit further includes a relative position value generator circuit which produces a plurality of position values representing the position of each detection and transition sample in a symbol of the input data, the position values being determined in accordance with both the estimated symbol timing correction value produced by the clock loop error detection and loop filter circuit and in accordance with a known distance between successive samples.
The demodulator circuit also includes a gate generator circuit which receives the plurality of position values and produces timing gate signals in accordance with a classification scheme. According to the present invention, when a sample is classified as being left of the mid-point, the next sample is forced to be classified as right of the mid-point, regardless of the position count. Similarly, after a sample that is classified as being before the transition point, the next sample will always be classified as after the transition point, regardless of the position count.
The position values, together with the timing gate signals, are then used by various circuits of the demodulator circuit in order to control the selection of samples.
According to another aspect of the invention, the demodulator circuit may also be provided with a switching controller circuit which controls the demodulator circuit so that a plurality of channels may be processed by the demodulator circuit. According to one aspect of the invention, each of the just-mentioned circuits in the demodulator circuit may be constituted by a plurality of shared register circuits which each include a register, an output device and a random access memory which stores data input from the register during a write cycle of the random access memory and outputs data to the output device for processing and storage in a subsequent register during a read cycle of the random access memory.
The invention is also directed to a method of implementing and operating the demodulator described above.
REFERENCES:
patent: 5228062 (1993-07-01), Bingham
patent: 5313496 (1994-05-01), de Goede
patent: 5317734 (1994-05-01), Gupta
patent: 5459473 (1995-10-01), Dempster et al.
patent: 5537435 (1996-07-01), Carney et al.
patent: 5812334 (1998-09-01), Behrens et al.
Sayegh Soheil I.
Thomas James R.
Al-Beshrawi Tony
Chin Stephen
Comsat Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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