Boots – shoes – and leggings
Patent
1982-09-23
1986-12-16
Heckler, Thomas M.
Boots, shoes, and leggings
G06F 1342
Patent
active
046301933
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a multi-master processor bus which permits multiple microprocessors to communicate freely and inexpensively among themselves and various system resources. The invention permits easy expansion of functionality without modification of the individual processors and thus contemplates a very large scale computer system which can be built with a number of microprocessors.
THE PRIOR ART
The current state of the art technology allows only one to three processors to share a common system bus at the same time. Many of the bus structures in use today cannot even handle two processors without elaborate and expensive direct memory access (DMA) controllers, bus multiplexers and conflict resolvers.
Current microprocessor system buses are extremely wasteful in exploiting bus bandwidth. When a microprocessor accesses a typical system bus, it will wait on the bus until it receives or transmits the desired data. Most microprocessors have a bus cycle time of 500 to 1000 nsec. The actual data transfer could be accomplished within a fraction of that period. While a given processor is waiting for its data, it effectively locks out any other processors from using the bus.
THE ADVANCE OF THE PRESENT INVENTION
The multi-master processor bus of the present invention allows a large number (N) of processors to share a common system bus simultaneously without conflict and requires very little or no hardware overhead and very simple software that is embedded within each processor board. Each processor board is identical to each other in every respect, mechanically, electrically, and in firmware (if desired). A limit of eight master processors is typically chosen as a practical guide for assembly and test, but additional processors theoretically could be added to the system.
In accordance with the present invention the backplane that supports the bus is a simple standard network of wires that interconnects the various system modules. The system controller is made up of only two standard medium scale integration chips (MSIs) that can be integrated within the backplane.
The multi-master processor bus greatly increases the effective bandwidth of the system bus by employing a time multiplex packet driven architecture. The architecture allows unlimited global system resources, it allows each master processor unlimited private resources and allows multiple multi-master processor buses to be interconnected.
THE PRESENT INVENTION
More specifically, the present invention relates to a multi-master processor bus for interconnecting a plurality of processor modules comprising a plurality of cables each having a plurality of connecting lines to a plurality of sets of processor module terminals for attachment to a plurality of processor modules. Cables are supplying at least the following purposes: interrupt request; interrupt acknowledge; address and control; time slice vector and clock; and data. Clock means provides periodic impulses and counter means is assocated with the clock to count the impulses and generate a multiphase clock. The cable connections include cables and means for interconnecting each of the modules in series daisy chain fashion to both the interrupt request and interrupt acknowledge cables.
The invention also contemplates a method of processing data using a plurality of master processors which are provided with parallel cable connections to a bus. By the method one of the master processor is selected arbitrarily to be the master master processor to designate which processor shall be active, accept data or output data to other processors. Time slice signals are then provided to sequentially grant access to the bus by each of the processors one at a time in a repetitive sequence.
DRAWINGS OF A PREFERRED EMBODIMENT OF THE INVENTION
A preferred embodiment of the present invention is illustrated in the accompanying drawings in which:
FIG. 1 is an overall block schematic diagram of the multi-master processor bus in the connection system, showing interconnections of a plurality of processors
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Short, Kenneth L., Microprocessors and Programmed Logic, Prentice Hall, Inc., Englewood Cliffs, NJ 1981, pp. 254-256.
"Rapid Bus Multiprocessor System" by Zoccoli and Sanderson, Nov. 1981 issue of Computer Design, pp. 189-200.
Heckler Thomas M.
Textron Inc.
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