Multiplierless digital filtering

Details Multiplierless digital filtering Multiplierless digital filtering

1998-08-07

2001-03-13

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S313000

Reexamination Certificate

active

06202074

ABSTRACT:

BACKGROUND
The present invention relates to digital filtering techniques, and more particularly, to filtering techniques that avoid the use of multipliers.
In state of the art applications requiring decimation of a high-rate digital signal, such as a 1-bit signal generated by a sigma-delta modulator, cascade-integrate-comb filters (CIC-filters) are used for a first decimation stage. These are then followed by a conventional finite impulse response (FIR) decimation filter stage. Decimation by N means that the filter output sample will be generated only once for every N data samples. Each filter output is a multi-bit value that is representative of the corresponding N data samples.
FIG. 1
is a block diagram of an exemplary prior art implementation of a three-stage CIC-filter that decimates the input signal by a factor of N. As can be seen from the figure, the CIC-filter consists of a number of accumulators
11
as a first stage, which is operated at the rate of a fast sampling clock
15
. The following decimation stage
13
then generates samples at the rate of a lower decimated clock
17
by supplying only every Nth sample at its output and leaving out the others. Finally, a third stage contains differentiators
19
operated at the decimated clock rate.
As all filter coefficients are set to 1, CIC-filters do not need multipliers. As a result, they can run at speeds limited by the speed of the adders (in the first stage). Thus, when very high data rates are involved, CIC-filters are used for the first decimation steps in order to lower the data rate sufficiently to enable FIR filters to be used. However, the sin(x)/x frequency domain characteristic of the CIC-filters must be compensated for by the subsequent FIR filters, which complicates the design of these FIR filters. For very fast applications, the adders in the CIC-filter are the speed limiting factor.
Also, the structure illustrated in
FIG. 1
is rather inflexible so that filter banks may be required if fast variability of the filter characteristic (and thus varying number of stages) is required. That further complicates the filter structure.
SUMMARY
It is therefore an object of the present invention to provide improved digital filtering techniques.
In accordance with one aspect of the present invention, the foregoing and other objects are achieved in filtering apparatuses and methods that include receiving an L-bit block of 1-bit data samples, wherein L is greater than 1; and using the L-bit block of 1-bit data samples to select a corresponding one of
2
L
filter output values.
In accordance with another aspect of the invention, using the L-bit block of 1-bit data samples to select a corresponding one of
2
L
filter output values comprises using each of the L 1-bit data samples to determine a product value by alternatively selecting a corresponding filter coefficient or a negation of the filter coefficient; and generating the corresponding one of the
2
L
filter output values by adding together the L product values.
In yet another aspect of the invention, using the L-bit block of 1-bit data samples to select a corresponding one of
2
L
filter output values may alternatively comprise using the L-bit block of 1-bit data samples to address an addressable memory having stored therein the
2
L
filter output values, wherein each L-bit block of 1-bit data samples addresses a corresponding one of the
2
L
filter output values, thereby causing the addressed filter output value to be supplied at an output of the addressable memory. The
2
L
filter output values may represent
2
L
possible sums of L values, each value alternatively representing one of L filter coefficients or a negation of the one of L filter coefficients. Alternatively, each value may alternatively represent one of L filter coefficients or zero.
In other aspects of the invention, the single addressable memory can be replaced by several smaller memories, each receiving, as an address, a corresponding subset of bits from the L-bit block of 1-bit data samples. The outputs of the smaller memories are combined to generate the filter output value.
In still another aspect of the invention, using the L-bit block of 1-bit data samples to select a corresponding one of
2
L
filter output values may comprise using a group of m(i) bits of the L-bit block of 1-bit data samples to address a corresponding one of a number, K, of addressable memories, wherein 1≦i≦K, and wherein each addressable memory has stored therein
2
m(i)
partial filter output values, wherein each group of m(i) bits addresses a corresponding one of
2
m(i)
partial filter output values, thereby causing an addressed partial filter output value to be supplied at an output of the addressable memory. The corresponding one of the
2
L
filter output values are then generated by combining the partial filter output values from the K addressable memories. In some embodiments, m(i)=L/K for 1≦i≦K. That is, each of the K memories may receive the same number, L/K, of bits from the L-bit block of 1-bit data samples.
In yet another aspect of the invention, one or more N-bit blocks of 1-bit data samples are latched in a cascaded latch arrangement, wherein each of the latching steps is performed in response to a decimated clock signal that is asserted once for every N assertions of a sampling clock rate. Latched values from each of the one or more cascaded latches are grouped together so as to form at least part of the L-bit block of 1-bit data samples that are received.
In still another aspect of the invention, an additional latch is provided that receives and latches one or more 1-bit data samples from an output of a last one of the one or more cascaded latch arrangement, wherein the additional latch operates in response to the decimated clock signal. A latched value from the additional latch is used to form at least part of the L-bit block of 1-bit data samples that are received. The additional latch is useful when L is not an integer multiple of N.
In yet another aspect of the invention, the 1-bit data samples are serially received under the control of a sampling clock. An N-bit block of the serially received 1-bit samples are then supplied for use in a first one of the cascaded latches.


REFERENCES:
patent: 3814917 (1974-06-01), Nussbaumer
patent: 3822404 (1974-07-01), Croisier et al.
patent: 5528527 (1996-06-01), Iwata et al .
patent: 5596609 (1997-01-01), Genrich et al.
patent: 5838725 (1998-11-01), Gurusami et al.
“FIR Filter for Processing Sigma-Delta Modulator Outputs,” IBM Technical Disclosure Bulletin, vol. 33, No. 6B, Nov. 1990, pp. 168-171, XP000108833.
N. Kouvaras, et al., “Realisation of Nonrecursive Delta-Modulation Filters using Look-up Tables,” I.E.E. Proceedings-G/Electronic Circuits and Systems, vol. 134, No. 3, Jun. 1987, pp. 127-131, XP002092360.
Shengping Yang, et al., “A Tunable Bandpass Sigma-Delta A/D Conversion for Mobile Communication Receiver,” IEEE Vehicular Technology Conference, vol. 2, 1994, pp. 1346-1350.
Richard Schreier, “An Empirical Study of High-Order Single-Bit Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 40, No. 8, Aug. 1993, pp. 461-466.

Affiliated with

Also associated with

Rating

Multiplierless digital filtering does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplierless digital filtering, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplierless digital filtering will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2493190