Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-11-26
2001-03-06
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06198319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power-on circuit which is built in an IC (integrated circuit) device such as a synchronous IC memory.
2. Description of the Related Art
Conventionally, a power-on circuit is built in various IC devices, and a power-on circuit built in a synchronous IC memory is shown in FIG.
3
.
Referring to
FIG. 3
, the conventional power-on circuit shown includes a one-shot pulse generation circuit
50
for generating a single pulse signal P, and an output controlling circuit
52
for controlling an output terminal DQ to a high impedance state in response to the pulse signal P generated by the one-shot pulse generation circuit
50
. The power-on circuit further includes a mode discrimination circuit
54
.
The one-shot pulse generation circuit
50
includes a pair of p-channel FETs (field effect transistors)
501
and
502
and a resistor
503
connected in series, and an invertor
504
having an input terminal connected to a junction B between the FET
502
and the resistor
503
. A power supply voltage Vdd is applied to the drain of the FET
502
, and the source and the gate of the FET
501
are connected together. The FET
502
is connected at the drain thereof to the source of the FET
501
and at the source thereof to the junction B, and is grounded at the gate thereof. The pulse signal P is outputted from an output terminal of the invertor
504
.
The output controlling circuit
52
includes five invertor
521
,
523
a
,
523
b
,
524
a
and
524
b
, a pair of NAND gates
522
a
and
522
b
, and a pair of FETs
525
a
and
525
b.
FIG. 4
is a waveform diagram illustrating operation of the one-shot pulse generation circuit
50
. In the following, operation of the conventional power-on circuit is described with reference to
FIGS. 3 and 4
.
In
FIG. 4
, the power supply voltage Vdd is indicated by a solid line; the voltage V
B
at the junction B is indicated by an alternate long and short dash line; and the pulse signal P is indicated by a broken line. When a power supply switch not shown for the synchronous IC memory is turned on, microscopically the power supply voltage Vdd rises gradually. As the power supply voltage Vdd rises, also the voltage V
B
at the junction B rises gradually. The invertor
504
outputs a high level signal (H) when the voltage V
B
is equal to or lower than a threshold value Vth, but outputs a low level signal (L) when the voltage V
B
is higher than the threshold value Vth. Since microscopically also the output signal of the invertor
504
rises and falls gradually, the pulse signal P exhibits a triangular waveform.
If the pulse signal P changes to ‘H’ in level, then the output level of the output terminal of the invertor
521
changes to ‘L’. Consequently, since the ‘L’ level is inputted to one of a pair of input terminals of each of the NAND gates
522
a
and
522
b
, the output terminals of the NAND gates
522
a
and
522
output the ‘H’ level irrespective of whether the inputs to the other input terminals of them have the ‘H’ level or the ‘L’ level.
Accordingly, since the output terminals Qa and Qb of the mode discrimination circuit
54
have the ‘H’ level, the FETs
525
a
and
525
b
are both controlled to an off state. Consequently, the output terminal DQ exhibits a high impedance state.
Then, if the pulse signal P falls to the ‘L’ level, then the input signal level to one of the input terminals of the NAND gates
522
a
and
522
b
changes to the ‘H’ level. However, since the ‘L’ level remains inputted to the other input terminals of the NAND gates
522
a
and
522
b
, the output terminals of the NAND gates
522
a
and
522
b
continue to output the ‘H’ level. Accordingly, the high impedance state of the output terminal DQ is maintained.
Even after the power supply switch is turned on as described above, the mode discrimination circuit
54
does not operate until a clock signal CLK is inputted thereto. Consequently, it is unknown, that is, indefinite, whether the output terminals Qa and Qb exhibit the ‘H’ level or the ‘L’ level until the clock signal CLK is inputted to the mode discrimination circuit
54
after the power switch is turned on. Therefore, the power-on circuit keeps the output terminal DQ in a high impedance state until the clock signal CLK is inputted after the power supply switch is turned on.
If the clock signal CLK is outputted, then the mode discrimination circuit
54
operates in accordance with a command signal CMD inputted thereto from the body of the synchronous IC memory in which the power-on circuit is incorporated. In particular, the mode discrimination circuit
54
controls the output terminals Qa and Qb thereof to the ‘H’ level thereby to control the output terminal DQ to a high impedance state. Or, the mode discrimination circuit
54
controls the output terminal Qa to the ‘H’ level and controls the output terminal Qb to the ‘L’ level thereby to control the output terminal DQ to the ‘L’ level. Or on the contrary, the mode discrimination circuit
54
controls the output terminal Qa to the ‘L’ level and controls the output terminal Qb to the ‘H’ level thereby to control the output terminal DQ to the ‘H’ level.
In this instance, since the output terminal of the invertor
521
normally exhibits the ‘H’ level, one of the two input terminals of each of the NAND gates
522
a
and
522
b
always has the ‘H’ level. Consequently, the output of each of the NAND gates
522
a
and
522
b
exhibits the ‘L’ level if the input level to the other input terminal is ‘H’, but exhibits the ‘H’ level if the input level to the other input terminal is ‘L’. Consequently, the output controlling circuit
52
does not have an influence on the states of the output terminals Qa and Qb of the output controlling circuit
52
.
However, the conventional power-on circuit may possibly operate normally depending upon a rising condition of the power supply voltage. In particular, since the one-shot pulse generation circuit generates only one pulse signal making use of a rising edge of the power supply voltage, if the rising edge of the power supply voltage is steep or conversely much time is required for such rising of the power supply voltage, then the rising edge of the power supply voltage may not possibly be detected.
If the rising edge of the power supply voltage is not detected, then since the one-shot pulse generation circuit cannot generate a pulse signal normally, the high impedance state which is an initial state of the output of the IC cannot be assured. Therefore, when a controller which connects to the same bus as the IC effects a data reading operation before the IC starts its operation after a point of time immediately after the power supply voltage is made available, the read data and output data of the IC may possibly be outputted to the bus at the same time, thereby causing a trouble called bus fight.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power-on circuit which assures a high impedance state of a terminal of an IC until the IC starts its operation after a point of time immediately after a power supply voltage is made available to the IC.
In order to attain the object described above, according to the present invention, there is provided a power-on circuit built in an integrated circuit, comprising a successive pulse generation circuit for successively generating a pulse signal after a power supply voltage begins to be supplied to the integrated circuit, an output controlling circuit for controlling a terminal of the integrated circuit to a high impedance state while the pulse signal generated by the successive pulse generation circuit is inputted thereto, and a pulse signal interruption circuit for interrupting the pulse signal from being inputted to the output controlling circuit after a clock signal is inputted thereto.
When the power supply voltage begins to be supplied to the integrated circuit, the successive pulse generation circuits begins to successively generate a pulse signal. If the pulse signal is outpu
McGuireWoods LLP
NEC Corporation
Nguyen Linh
Tran Toan
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