Pipeline analog to digital (A/D) converter with relaxed...

Details Pipeline analog to digital (A/D) converter with relaxed... Pipeline analog to digital (A/D) converter with relaxed...

2000-02-17

2001-09-25

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S162000

Reexamination Certificate

active

06295016

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to pipeline analog to digital (A/D) converters and, more particularly, to circuit and timing at the initial stages of the pipeline A/D converters.
BACKGROUND
There is an ever present demand for analog to digital (A/D) converters that accurately convert an analog voltage signal into a digital representation. There is also a need for faster A/D converters that use less power and have smaller areas on an integrated circuit. Oftentimes, a conventional A/D converters sacrifice accuracy in favor of meeting speed, power consumption and size demands.
FIG. 1
illustrates a conventional pipeline analog to digital (A/D) converter
10
. The A/D converter
10
converts an analog electrical input signal (V
IN
) into a digital representation of the analog signal (D
OUT
) The illustrated example is a 4-bit A/D converter, but it should be understood that a resolution of more or less bits may be implemented with the addition or removal of converter stages. Therefore, the resolution of the A/D converter will sometimes be referred to an N-bit A/D converter, where N represents the number of digital output bits. The A/D converter
10
has an analog signal input
12
provided on an initial stage. The initial stage is a sample-and-hold amplifier (SHA)
14
. The SHA
14
samples the analog input signal and holds the sampled voltage, or V
s/h
, for the next stage of the pipeline A/D converter
10
at an SHA output
16
. The stage following the SHA
14
is a multiplying digital to analog converter (MDAC)
18
. MDAC
18
stages are added to the pipeline to increase the number of output bits.
With additional reference to
FIG. 2
, each MDAC
18
has an analog input
20
and an analog output
22
. Each MDAC
18
performs analog to digital conversion of an MDAC input signal, V
I
, applied to the analog input
20
. Each MDAC
18
also calculates an amplified residue signal, V
res
, which is output for the next stage at the analog output
22
. The number of MDAC
18
stages is determined by the desired resolution of the A/D converter
10
, or the value of N. The number of MDAC
18
stages is equal to N minus two. In the example, the resolution is four bits. Therefore there are two MDAC
18
stages, referred to as MDAC, (reference numeral
24
) and MDAC
2
(reference numeral
26
). The SHA output
16
is connected to the analog input
20
of MDAC
1
. The analog output
22
of MDAC
1
is connected to the analog input
20
of MDAC
2
. Therefore, the V
I
of each MDAC
20
, other than MDAC
1
which receives V
s/h
, is the V
res
of the preceding MDAC
18
, also referred to herein as V
resm
where m stands for the MDAC
18
generating the output signal.
The analog output
22
of the last MDAC
18
, which is MDAC
2
in the example, is connected to an input
28
of a last stage
30
. The last stage
30
, which will be discussed in more detail below, has no analog output.
Each MDAC
18
and the last stage has two digital outputs
32
,
34
for providing one bit of resolution and one bit for correcting error. The bits are generically referred to as b
1
and b
0
or, for a specific MDAC
18
, are referred to as b
m1
and b
m0
where m stands for the MDAC
18
generating the output signal or the last stage
30
. It is noted that MDAC
1
generates b
11
and b
10
with some degree of error, MDAC
2
generates b
21
and b
20
with some degree of error and so forth. With additional reference to
FIG. 4
, the last stage
30
of the illustrative four bit A/D converter
10
generates b
3, and b
31
where b
30
, is the least significant bit (LSB) and b
3
is used to correct error generated by MDAC
2
by adding b
31
and b
20
. As illustrated, b
21
is added to b
10
to correct error generated by MDAC
1
. In general, therefore, b
m1
is used to correct the error generated by MDACm
m−1
.
Still referring to
FIGS. 1 and 2
, each MDAC
18
has a 1.5 bit analog to digital converter (ADC)
36
for generating b
1
and b
0
from V
I
. Table 1 is a definition table for the values of b
1
and b
0
with respect to V
I
for the MDAC
18
. It is noted that ±V
r
is the full scale range of the ADC
36
.
TABLE 1
Input Voltage Range (V
I
)
b
1
b
0
V
I
< −V
r
/4
0
0
−V
r
/4 < V
I
< +V
r
/4
0
1
V
I
> +V
r
/4
1
0
Once b
1
and b
0
are generated by the ADC
36
they are output at digital outputs
32
,
34
and also input into a 1.5 bit digital to analog converter (DAC)
38
. The DAC
38
converts b
1
and b
0
into an analog signal, or V
DAC
, used in the calculation of V
res
. Table 2 is a definition table for the value of V
DAC
with respect to b
1
and b
0
for the MDAC
18
.
TABLE 2
b
1
b
0
V
DAC
0
0
−V
r
/2
0
1
0
1
0
+V
r
/2
The MDAC
18
generates V
res
by subtracting V
DAC
from V
I
with an adder
40
and amplifying the summed value with an amplifier
42
having a gain of two. With additional reference to
FIG. 3
, the characteristics of the MDAC
18
are illustrated.
FIG. 3
graphs V
I
versus V
res
and illustrates the values of b
1
and b
0
over the range of values for V
I
.
The last stage
30
is a two bit analog to digital converter (ADC) for converting the last stage's input voltage, V
I
, into a two bit digital value. Therefore, similar to the MDACs
18
, the last stage has two digital outputs
32
,
34
respectively providing b
1
and b
0
. The b
0
provided at the second digital output
34
for the last stage
30
represents the least significant bit of the digital output of the A/D converter
10
. Alternatively, the last stage
30
can be implemented with an MDAC
18
without connecting the output
22
to any other stage. Table 3 is a definition table for the values of b
1
and b
0
with respect to V
I
for the two bit last stage
30
.
TABLE 3
Input Voltage Range (V
I
)
b
1
b
0
V
I
< V
r
· ¾
0
0
−V
r
· ¾ < V
I
< −V
r
/4
0
1
−V
r
/4 < V< +V
r
/4
1
0
V
I
> +V
r
/4
1
1
The digital outputs of the MDACs
18
and the last stage
30
are input into a digital logic correction circuit
44
. The digital logic correction circuit
44
generates the digital output, D
OUT
, of the A/C converter
10
. The digital output is a series of bits, or D
N−1
to D
0
. In the example, N is four bits. Therefore, the digital output is D
3
, D
2
, D
1
and D
0
where D
3
is the most significant bit (MSB) and D
0
is the least significant bit (LSB). The digital logic correction circuit
44
corrects error caused by inaccurate thresholds in the 1.5 bit ADC
36
of the MDACs
18
and the two bit ADC of the last stage
30
. As long as the individual thresholds deviate no more than V
r
/4 from an ideal value, then the error can be corrected by adding shifted digital outputs of each of the stages.
FIG. 4
depicts a shifting operation of the digital error correction circuit
44
. It is noted that S is the number of stages of the A/D converter
10
excluding the SHA
14
and the last stage
30
. In other words, S is the number of MDACs
18
in the pipeline AID converter
10
.
FIG. 5
is a graph of the characteristics of the 4-bit A/D converter
10
illustrated in
FIG. 1
, under the condition that the thresholds for the 1.5 bit ADC
36
of the MDACs
18
and the 2 bit ADC of the last stage
30
deviate no more than V
r
/4. It is noted that ±V
R
is the full scale range of the A/D converter
10
. It is also noted that an analog input voltage of zero volts is defined as the center of digital
1000
. However, if the thresholds of the two bit ADC of the last stage
30
are +V
r
*¾, +V
r
/4 and−V
r
/4, rather than the thresholds shown in Table 3, the A/D conversion curve illustrated in
FIG. 5
will move one LSB to the right resulting in analog input voltage of zero volts being defined as the center of digital
0111
.
Referring to
FIGS. 2 and 13
, the timing of the A/D converter
10
will be discussed. The A/D converter
10
has a bias and reference generator (not shown) and a clock generator (not shown). The bias and reference generator genera

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