Semiconductor device having metal interconnection comprising...

Details Semiconductor device having metal interconnection comprising... Semiconductor device having metal interconnection comprising...

1995-08-28

2001-08-14

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C438S643000, C438S644000, C438S645000, C438S649000, C438S655000

Reexamination Certificate

active

06274932

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a metal interconnection.
2. Description of the Related Art
Some of known conventional semiconductor devices are disclosed in U.S. patent application Ser. Nos. 4,789,648 and 4,944,836. The first conventional semiconductor device will be described with reference to
FIGS. 1A and 1B
and the second conventional semiconductor device will be described with reference to
FIGS. 2A
to
2
E.
(a) First Conventional Semiconductor Devices
First, the semiconductor device described in U.S. patent application Ser. No. 4,789,648 (hereinafter called the “first prior art example”) will be discussed with reference to
FIGS. 1A and 1B
.
FIGS. 1A and 1B
are vertical crosssectional views illustrating the fabrication process for this semiconductor device (first prior art example) consisting of steps
1
A and
1
B.
According to the first prior art example, as shown in
FIG. 1A
, an insulating film
104
a
as a silicon dioxide film is formed on a silicon substrate
101
by chemical vapor deposition (hereinafter referred as CVD) or the like, a groove pattern is formed by known techniques, and then an aluminum film (Al film)
114
as a conductive film is formed by sputtering.
At this time, the thickness of the insulating film
104
a
is set equal to the thickness of the necessary interconnection film plus the thickness of the conductive film. A silicon nitride which serves as a stopper at the later step of polishing the metal film may be formed on the insulating film
104
a.
Subsequently, the Al film
114
is polished and removed by chemical-mechanical polishing (hereinafter called “CMP”) using a slurry consisting of alumina (Al
2
O
3
)-added deionized water or an Al
2
O
3
-added nitrate solution, yielding a groove interconnection structure which has a groove pattern filled with an interconnection material (Al film
114
), as shown in FIG.
1
B.
(b) Second Conventional Semiconductor Devices
Next, the semiconductor device described in U.S. patent application Ser. No. 4,944,836 (hereinafter called the “second prior art example”) will be discussed with reference to
FIGS. 2A
to
2
E.
FIGS. 2A-2E
are vertical cross-sectional views illustrating the fabrication process for this semiconductor device (second prior art example) consisting of steps A to E.
According to the second prior art example, as shown in
FIG. 2A
, an insulating film
104
a
and an underlying Al interconnection
112
are formed using known techniques, an insulating film
104
b
(which may be a silicon dioxide film) is formed on the surface of the resultant structure, and a stopper
113
of Al
2
O
3
is then formed in a predetermined region by lithography, etching and the like.
Then, an insulating film
104
c
as a silicon dioxide film is formed on the stopper
113
and the insulating film
104
b
, as shown in FIG.
2
B.
Next, as shown in
FIG. 2C
, the insulating film
104
c
and insulating film
104
b
are patterned by selective etching using a resist (not shown) as a mask to form an interlayer contact hole
105
which reaches the underlying Al interconnection
112
.
As the stopper
113
is not etched at this time, only that portion of the insulating film
104
b
which lies under the opening of the stopper
113
is removed.
Subsequently, an Al film
114
is formed on the entire surface as shown in
FIG. 2D
by a known method like sputtering.
Then, the Al film
114
is polished and removed by CMP, yielding a groove interconnection structure which has the Al-filled interlayer contact hole
105
and an Al-filled groove pattern, as shown in FIG.
2
E.
(c) Third Conventional Semiconductor Devices
Another known conventional semiconductor device is described in “Proceedings of 1993 VLSI Multilevel Interconnection Conference, pp. 15-21 (1993)” (hereinafter called the “third prior art example”). This third prior art example will now be discussed with reference to
FIGS. 3A
to
3
E, which are vertical cross-sectional views illustrating the fabrication process for this example.
According to the third prior art example, as shown in
FIG. 3A
, first, an insulating film
104
a
of PI 5180 (polyimide resin) is formed 500 to 1000 nm thick on a silicon substrate
101
by rotational coating.
Next, a stopper
113
is formed of a silicon nitride film on the top of this insulating film
104
a
by a plasma CVD technique.
Then, a photoresist
116
to be an etching mask is formed in a predetermined region as shown in
FIG. 3B
using a lithography technique.
As shown in
FIG. 3C
, the stopper
113
and the insulating film
104
a
are etched by reactive ion etching using this photoresist
114
as a mask, forming a groove pattern for interconnection. Then, the photoresist
116
is removed.
Next, as shown in
FIG. 3D
, a tantalum film (Ta film)
106
a
is formed by sputtering, followed by the formation of a copper film (Cu film)
109
a
on the Ta film
106
a
to bury the interconnection groove pattern.
Then, as shown in
FIG. 3E
, the Cu film
109
a
and the Ta film
106
a
are removed by a known CMP process called “Damascene process ” in such a way that the Cu film
109
a
and Ta film
106
a
remain only inside the interconnection groove pattern. At this time, the stopper
113
serves as a stopper layer in the polishing step because the polishing speed of the stopper
113
on the insulating film
104
a
is slower than those of the Cu film
109
a
and Ta film
106
a.
According to the third prior art example, a semiconductor device having an interconnection whose main conductive layer is made of Cu is fabricated through those steps A to E.
(d) Fourth Conventional Semiconductor Devices
A further known conventional semiconductor device is described in Unexamined Japanese Patent Publication No. Sho 63-207153 (hereinafter called the “fourth prior art example”). This example will now be discussed with reference to
FIGS. 4A
to
4
F which are vertical cross-sectional views illustrating the fabrication process consisting of steps
4
A to
4
B.
According to the fourth prior art example, as shown in
FIG. 4A
, an insulating film
104
a
constituted of a silicon dioxide film is formed on a silicon substrate (not shown).
Subsequently, an underlying Al interconnection
112
of 1.0 &mgr;m in thickness is formed using a known technique, and an insulating film
104
b
constituted of a PSG film with a thickness of 1.0 to 1.5 &mgr;m is formed on the entire surface of the resultant structure.
Then, an upper lying Al interconnection
115
having a thickness of 1.0 &mgr;m is formed on the insulating film
104
b
as shown in FIG.
4
B.
Next, as shown in
FIG. 4C
, a stopper
113
made of a silicon nitride film of 200 nm thick is formed on the entire surface of the resultant structure by a plasma CVD technique.
Subsequently, the stopper
113
, the upper lying Al interconnection
115
and the insulating film
104
b
are partially removed using a resist (not shown) as an etching mask to form an interlayer contact hole
105
in the portion where the underlying Al interconnection
112
crosses the upper lying Al interconnection
115
, as shown in FIG.
4
D.
Single positioning is sufficient for opening this hole, and the opening need not be made particularly narrow and should have a diameter about the same as the widths of those interconnections. Therefore, the precision of the positioning need not be particularly high.
Next, an Al film
114
is formed 2000 to 3000 nm thick by downflow vapor deposition, as shown in FIG.
4
E.
Then, the Al film
114
on the stopper
113
is polished out, yielding a structure with the Al film
114
buried in the interlayer contact hole
105
, as shown in FIG.
4
F.
The first to fourth prior art examples have the following shortcomings.
For the first prior art example (the semiconductor device disclosed in U.S. patent application Ser. No. 4,789,648), the point of exposure of the insulating film
104
a
in the CMP process is the end of the polishing (see FIG.
1
B). It is therefore easy to detect the end by a change in electric capacitance

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