Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1997-05-30
2001-01-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185130
Reexamination Certificate
active
06175520
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to nonvolatile semiconductor memory devices, and more particularly to circuits for applying a programming voltage to memory cells within such devices.
BACKGROUND OF THE INVENTION
Electrically programmable read-only memories (EPROMs) include “UVEPROMs,” conventional EEPROMs, and “flash” EEPROMs (also referred as flash EPROMs). In all of the above type EPROMs, memory cells are programmed by applying selected voltages to the terminals of the memory cells.
FIG. 1
sets forth a conventional one transistor (“1-T”) EPROM cell. Cells of this general configuration are utilized in both UV-EPROMs and certain types of “flash” EPROMs. The 1-T cell is designated by the general reference character
1
, and is shown to be formed on a semiconductor substrate
2
of p-doped silicon. The cell
1
includes an n-doped source region
3
and an n-doped drain region
4
formed within the substrate
2
. A floating gate
5
and a control gate
6
are formed on the surface of the substrate
2
. The floating gate
5
is separated from the substrate
2
by a thin dielectric layer (referred to herein as a tunnel dielectric
7
). In addition, the floating gate
5
is separated from the control gate
6
by another dielectric layer (referred to herein as an interpoly dielectric
8
, as both the floating gate and control gate are commonly formed from polycrystalline silicon). The cell
1
of
FIG. 1
is shown in a typical program condition. A first program voltage (Vp) is applied to the drain
4
, a second program voltage (Vpp) is applied to the control gate
6
, and the source
3
is grounded. Vp and Vpp are typically positive voltages, with Vpp being in the range of 12V and Vp being in the range of 5V. Electrons are accelerated from the source
3
toward the drain
4
, and due to the field created by Vpp on the control gate
6
, injected through the tunnel dielectric
7
and into the floating gate
5
. At the very start of the programming operation the cell
1
draws a relatively large amount of source-drain current, but as charge accumulates in the floating gate
5
, the threshold voltage of the cell
1
rises, and this current drops in magnitude.
The cell current versus drain voltage relationship of a typical 1-T cell for a programming operation is set forth in FIG.
2
. As shown in
FIG. 2
, the current (Ids) rises to a high point (a “knee”
20
), and then drops suddenly as the cell is programmed. Also set forth in
FIG. 2
is a representation of three different program “load lines”
21
a
-
21
c
. The program load lines represent inherent impedance in the path from the program voltage source to the cell that is to be programmed. Load line
21
a
represents an undesirable case of a load line that is too high, and falls below the knee
20
. In such a case the drain voltage will never be high enough to program the cell. Load line
21
b
represents a marginal load line; one that never falls below the knee
20
, but is so close to the knee
20
that process variations may result in too high a load line for selected cells. Load line
21
c
represents a “good” load line that remains above the programming curve with sufficient margin to ensure proper programming of the cells.
To illustrate the origins of load line impedance, a portion of a prior art EPROM architecture is set forth in FIG.
3
. The EPROM is designated by the general reference character
30
, and is shown to include a number of memory cell arrays
31
a
-
31
d
. Each memory cell array (
31
a
-
31
d
) includes a number of memory cells arranged in rows and columns. Within the array, cells in the same row are coupled to the same word line by their respective control gates, and cells in the same column are coupled to the same bit line by their respective drains. One cell
32
, one word line
33
and one bit line
34
of array
31
a
are illustrated in FIG.
3
. The EPROM
30
includes a program voltage source
35
for supplying a program voltage to selected memory cells. According to well understood techniques the program voltage source
35
can be a positive supply voltage, or an even higher voltage generated from a supply voltage by way of charge pumps circuits, or the like. The program voltage is coupled from the program voltage source
35
to column selectors (
36
a
-
36
d
) of each array (
31
a
-
31
d
) by data lines, one of which is shown as item
37
in FIG.
3
. According to a supplied address, and input data stored in latch
38
the column selectors (
36
a
-
36
d
) couple the program voltage to selected bit lines, and thus to the drains of selected cells. The entire program voltage path from the program voltage source
35
to the drains of selected cells possesses an inherent impedance. The contacts, metallization(s) and/or diffusions included in the data lines all contribute to the impedance. In addition, bit lines and column selectors, particularly the active devices within the column selectors, further introduce impedance in the program voltage path.
Manufacturing technology improvements can also increase load line impedance. The use of lower supply voltages, smaller manufacturing geometries, and higher density devices, all contribute to the difficulty of providing an adequate load line response in programming EPROM devices. When used as the programming voltage, a lower supply voltage requires less load line impedance to adversely affect program operations, particularly if the cell programming characteristics cannot be scaled down in the same proportion. Smaller geometries can result in higher impedance interconnects, and higher impedance in active devices. Higher density devices can require longer interconnects to provide the programming voltage to the cells at the far end of the device, and thus introduce more impedance to the load line.
U.S. Pat. No. 4,999,812 issued to Allaaeldin Amin discloses a flash EPROM memory wherein a relatively high programming voltage for the cells of the memory is applied directly to the array by way of the flash EPROM cell sources. Such an approach can lead to faster read times, but may have some drawbacks in other modes of operation. It is noted that the Amin architecture includes a line impedance created by the path from the drain of the memory cells to ground. Further, the common source lines present a relatively large capacitive node, which can result in large discharge times.
U.S. Pat. No. 5,495,442 issued to Cernea et al. discloses an EEPROM with a “bit line voltage regulator” disposed between the bit line selection circuits and the bit lines. Programming voltage is supplied via sense amps through the bit line selection circuits. The path of the sense amplifier is interrupted in the case of an overvoltage condition on the bit lines.
U.S. Pat. No. 5,173,874 issued to Hiroyaki Kobatake discloses an EPROM in which a programming voltage (Vpp) is supplied to write circuits (one write circuit for each I/O). Separate interconnects are used to supply Vpp to write circuits and a voltage divider circuit, so that voltage drops introduced by interconnect are not introduced to the voltage dividing circuit.
U.S. Pat. No. 5,469,384 issued to Timothy M. Lacey on discloses a nonvolatile memory circuit that includes a load line circuit having two different impedance paths. One path is enabled to program one bit. A second, lower impedance path is used to program multiple (four) bits.
U.S. Pat. No. 5,398,203 issued to Bruce Prickett, Jr. discloses an EPROM programming circuit in which the current supplied to bit lines during programming is limited by a device in the load line that is placed into a linear mode of operation when bit line currents exceed desired levels.
U.S. Pat. No. 5,553,020 issued to Keeney et al. discloses a flash EEPROM device wherein the gate voltage is ramped to limit programming current.
FIG. 4
sets forth a prior art arrangement in which a combination of a local sense amplifier, program load circuit, and data latch are provided for each array. One array is designated as reference character
40
. A column selector
41
is disposed adjacent to th
Ray Abhijit
Reddy T. Damodar
Alliance Semiconductor Corporation
Limbach & Limbach LLP
Nelms David
Tran M.
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