Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1997-08-29
2001-09-04
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S059000, C257S072000, C257S350000
Reexamination Certificate
active
06285041
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin-film transistor and a fabrication method thereof and more particularly, to a thin-film transistor that is capable of a highly reliable operation for use as a liquid crystal display (LCD) device and others and that is readily fabricated, and a fabrication method of the transistor.
2. Description of the Prior Art
Unlike conventional monolithic transistors that are formed in the inside of a semiconductor substrate, thin-film transistors are fabricated by stacking several thin films on a substrate. Therefore, the thin-film transistors have a simple and easy-to-fabricate configuration compared with the monolithic transistors. As a result, the thin-film transistors have been in widespread use as, for example, switching elements in a large-sized electronic device such as an LCD device.
Further, the simplicity of the device configuration and fabrication method of the thin-film transistors makes it possible to fabricate various applied products at low cost, which contributes to popularization of them on the market.
In recent years, the above simplicity of the thin-film transistors has been further improved and progressed.
Specifically, the basic components of a thin-film transistor are a substrate, a semiconductor thin film in which a conductive channel is formed on operation, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The source and drain electrodes, which are located apart from each other on a same side of the semiconductor film, are electrically connected to the semiconductor film. The gate insulating film is located on an opposite side of the semiconductor film to the source and drain electrodes. The gate electrode, which is located on the same side of the semiconductor film as the gate insulating film, is opposite to the semiconductor film through the gate insulating film. The conductive channel is formed in the gate-side surface region of the semiconductor film under application of a proper gate voltage.
The semiconductor thin film is typically formed by an undoped (or, i-type) semiconductor material. In this case, there is the need for interposing an n
+
-type semiconductor film between the i-type semiconductor film and the opposing source and drain electrodes. The n
+
-type semiconductor film is used to form source and drain contact regions between the undoped semiconductor film and the source and drain electrodes, respectively. The source and drain contact regions provide good Ohmic contacts therebetween.
From this point of view, various contrivances have been continued to minimize the number of necessary films and the number of necessary fabrication processes.
When the n
+
-type semiconductor film serving as the source and drain contact regions is provided, the source and drain electrodes are short-circuited to each other by the n
+
-type semiconductor film. Therefore, it is necessary to add a process of selectively removing the n
+
-type semiconductor film by etching in a back channel section between the source and drain electrodes.
However, if the n
+
-type semiconductor film is formed to be extremely thin, the etching process for selectively removing the back channel section of the n
+
-type semiconductor film can be omitted without arising any problem about the off-resistance of the thin-film transistor. This knowledge was disclosed in the Japanese Non-Examined Patent Publication No. 59-172774 published in 1984.
FIG. 1
shows a first conventional thin-film transistor of the inverted staggered (or, bottom gate) type, which is disclosed in the Japanese Non-Examined Patent Publication No. 59-172774.
In
FIG. 1
, a gate electrode
1102
is formed on an insulating substrate
1101
. A gate insulating film
1103
is formed on the substrate
1102
to cover the gate electrode
1102
. An undoped or i-type amorphous silicon film
1104
is formed on the gate insulating film
1103
. An n
+
-type amorphous silicon film
1105
for source and drain contact regions is formed on the i-type amorphous silicon film
1104
. A drain electrode
1106
and a source electrode
1107
are formed on the n
+
-type amorphous silicon film
1105
to be apart from each other.
FIG. 2
shows a second conventional thin-film transistor of the staggered (or, top gate) type, which is disclosed in the Japanese Non-Examined Patent Publication No. 59-172774.
In
FIG. 2
, a drain electrode
1106
and a source electrode
1107
are formed on an insulating substrate
1101
to be apart from each other. An n
+
-type amorphous silicon film
1105
for source and drain contact regions is formed on the substrate
1101
to cover the drain and source electrodes
1106
and
1107
. The n
+
-type amorphous silicon film
1105
is contacted with the substrate
1101
in a back channel section
1204
between the drain and source electrodes
1106
and
1107
. An undoped amorphous silicon film
1104
is formed on the n
+
-type amorphous silicon film
1105
. A gate insulating film
1103
is formed on the undoped amorphous silicon film
1104
. A gate electrode
1102
is formed on the gate insulating film
1103
.
In
FIGS. 1 and 2
, the n
+
-type amorphous silicon film
1105
is extremely thin to give a high off-resistance of 10
9
&OHgr; or higher between the source and drain electrodes
1107
and
1106
. The n
+
-type amorphous silicon film
1105
is not removed in the back channel section
1204
. In other words, the n
+
-type amorphous silicon film
1105
is continuous from the drain electrode
1106
to the source electrode
1107
.
A third conventional thin-film transistor was disclosed in the Japanese Examined Patent Publication No. 6-22244 published in 1994 (which corresponds to the Non-Examined Patent Publication No. 62-81064 published in 1987). This transistor has phosphorus-doped regions in the respective surface regions of transparent source and drain electrodes and a transparent glass substrate. The phosphorus-doped regions are formed by exposing the source and drain electrodes and the substrate to phosphine (PH
3
) plasma. The phosphorus-doped regions have substantially the same action as that of the extremely-thin n
+
-type amorphous silicon film
1105
in
FIGS. 1 and 2
. Therefore, an etching process in the back channel section can be omitted while ensuring an Ohmic contact.
In detail, as shown in
FIG. 3
, a drain electrode
1106
and a source electrode
1107
, which are formed by patterning a transparent conductive film, are located on a transparent glass substrate
1141
to be apart from each other. The drain and source electrodes
1106
and
1107
include phosphorus-doped regions
1106
A and
1107
A in their tops, respectively. The substrate
1141
includes a phosphorus-doped region
1141
A in an exposed area between the drain and source electrodes
1106
and
1107
. The phosphorus-doped regions
1106
A,
1107
A, and
1141
A are formed by a plasma doping process of phosphorus.
A patterned undoped amorphous silicon film
1104
is formed on the substrate
1141
to partially cover the drain and source electrodes
1106
and
1107
. A patterned gate insulating film
1103
is formed on the undoped amorphous silicon film
1104
. A gate electrode
1102
is formed on the gate insulating film
1103
. A silicon nitride film
1108
is formed on the substrate
1141
to cover the drain and source electrodes
1106
and
1107
, the amorphous silicon film
1104
, the gate insulating film
1103
, and the gate electrode
1102
.
A phosphorus-doped region
1145
is formed in the amorphous silicon film
1104
in its bottom. The phosphorus-doped region
1145
extends along the interfaces of the amorphous silicon film
1104
with the opposing drain and source regions
1106
and
1107
and with the opposing substrate
1141
. The parts of the phosphorus-doped region
1145
located on the drain and source electrodes
1106
and
1107
serve as the Ohmic contact regions. The phosphorus-doped region
1145
is formed by diffusion or dopin
NEC Corporation
Ngo Ngan V.
Sughrue Mion Zinn Macpeak & Seas, PLLC
LandOfFree
Thin-film transistor having a high resistance back channel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thin-film transistor having a high resistance back channel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin-film transistor having a high resistance back channel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2491039