Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-03-23
2001-07-31
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S239000
Reexamination Certificate
active
06269049
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an improved output matrix for use in a controller for a generator system in a Dynamic Random Access Memory (DRAM) that is very flexible, and the functionality of which can be easily adjusted to the generator system and permit quick “last-minute-changes” in the controller's behavior.
BACKGROUND OF THE INVENTION
Modern DRAM chips have many different voltages (e.g., more than 10) on-chip that have to be generated by a plurality of generator circuits. These voltages include several reference voltages (e.g., for receiver circuits and for bias current generation) as well as several voltages that supply various functional blocks on the chip with operating current (e.g., voltages for sense amplifiers and word line drivers). All of these voltages are generated from one external source voltage by the plurality of generator circuits.
There are basically three operating modes which occur for the voltage generating circuits. These modes are (1) a normal operating phase, (2) a test and burn-in phase, and (3) a power-on phase. In each of these modes the generator system operates in a different way, and needs to be controlled in a specific way. A controller for the generator system has to ensure a proper coordination of all generator functions for each of the various modes. More particularly, once the external source voltage (VEXT) is applied to the DRAM chip, the generator system goes through a power-on phase. After the power-on phase, all voltages on the DRAM chip are stable, and the generator system (and the whole chip) enters the normal operating phase. For burn-in and for test purposes, a multitude of additional functions have to implemented into the generator system.
The problem is that the overall logic behavior of the generator system, and its controller, is relatively complex. This is especially true during a late phase of a design project as all of the sub-systems are being put together, and it is very likely that changes in the logic functionality of the controller have to be made. In a current one-Gigabit (GB) chip, known by the designation ZEUS DD
1
, logic control functions of a generator system therein were clearly separated from the voltage generating functions. The logic behavior of the generator system is implemented in a digital controller (a finite state machine). In order to realize a finite state machine, design and layout synthesis was used in the 1 GB Dynamic Random Access Memory (DRAM) chip. The logic behavior therein was specified in a truth table, and the concept was to create circuitry automatically within a short time by using the respective software tools. Thus, changes or corrections of the controller could theoretically be performed within a few hours, even in a late stage of a project.
Problems in existing solutions are that both design and layout synthesis tools do not provide a required solution to many problems for providing a flexible and fast controller design. For example, the design synthesis tool demanded a large amount of time for learning the handling and functionality of the tool, and this tool made manual corrections and working around of problems necessary. The layout synthesis tool created results that contained errors and required manual inspections and corrections. Additionally, one could not provide timing constraints to inputs to the tool for generating certain voltages which required manual checks of a synthesized layout for a critical path which then required manual corrections. Therefore, it is desirable to provide a technique where changes in the logic behavior of the controller is obtainable in a systematic and very quick manner.
The present invention provides a controller circuit for a generator system that is very flexible so that its functionality can easily be adjusted to a specific generator system to allow for last minute changes of the behavior of a generator circuit.
SUMMARY OF THE INVENTION
The present invention is directed to an output matrix for use in a controller for a generator system located on a chip such as a Dynamic Random Access Memory (DRAM). The specific behavior of the present controller and its output matrix is made very flexible so that its functionality can easily be adjusted to the specific associated generation system and permit quick “last-minute-changes” in the controller's behavior. Still further, the arrangement of the output arrangement is such that the current (bias) consumption is substantially zero during a “sleep” mode of the Controller.
Viewed from one aspect, the present invention is directed to a controller for controlling a generator system on a memory chip. The controller operates as a state machine in accordance with a state diagram including a plurality of X states. The controller comprises a state storage device and an output arrangement. The state storage device is responsive to input signals indicating a change in the state diagram from a current state to a next state of the plurality of X states for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. The output arrangement is responsive to the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state. The output signals are used for controlling the generator system, and the output arrangement provides substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.
Viewed from another aspect, the present invention is directed to a controller for controlling a remote system on a memory chip which operates in accordance with a state diagram including a plurality of X states. The controller comprises an evaluation arrangement, a state storage device, and an output arrangement. The evaluation arrangement is responsive at any instant of time for evaluating only one of a plurality of N input signals to the controller from remote devices in relation to only one of a plurality of X state signals. When a condition has been met wherein the one state signal and the one input signal have met predetermined logical conditions the evaluation arrangement generates one of a plurality of Y output signals that has a predetermined logical value for entering a next state in the state diagram. The state storage device is responsive to the one of a plurality of Y output signals having a predetermined logical value from the evaluation arrangement for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. Te true State signal is transmitted back to the evaluation arrangement indicating a change in the state diagram from a current state to a next state of the plurality of X states. The output arrangement is responsive to the true State signal and the complementary true State signal of the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state for controlling the generator system. The output arrangement has a configuration that provides substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.
Viewed from still another aspect, the present invention is directed to a method for controlling a generator system on a memory chip with a controller operating as a state machine in accordance with a state diagram including a plurality of X states. In a first step of the method, a revised plurality of X state output signals are generated comprising a true State signal and a complementary true State signal for a next state of the plurality of X states in a state storage device in responsive to input signals indicating a change in the state diagram from a current state to the next state of the plu
Braden Stanton C.
Infineon - Technologies AG
Phan Trong
LandOfFree
Method and apparatus for a flexible controller including an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for a flexible controller including an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for a flexible controller including an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2489003