Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-06-22
2001-09-04
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S437000
Reexamination Certificate
active
06284624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing the same and in particular to semiconductor devices with an element isolating trench region wherein compressive stress of the semiconductor substrate can be alleviated in a vicinity of the trench.
2. Description of the Background Art
A conventional semiconductor device manufacturing method and a semiconductor device obtained in accordance with the manufacturing method will now be described with reference to the drawings. Referring first to
FIG. 26
, thermal oxidation or the like is used to form a silicon oxide film
102
on a silicon substrate
101
. Chemical vapor deposition (CVD) or the like is used to form a silicon nitride film
103
on silicon oxide film
102
.
Referring then to
FIG. 27
, patterned photoresist (not shown) is provided on silicon nitride film
103
. The patterned photoresist is used as a mask to anisotropically etch silicon nitride film
103
and silicon oxide film
102
to expose a surface of silicon substrate
101
. The exposed silicon substrate
101
is further etched anisotropically to form a trench
104
of 3000 to 5000 Å in depth.
Referring now to
FIG. 28
, silicon substrate
101
is oxidized, e.g., at a temperature of 1100° C. in an oxygen ambient to form a silicon oxide film
105
on the silicon substrate
101
surface exposed in trench
104
. Referring then to
FIG. 29
, a Tetra Ethyl Ortho Silicate glass (TEOS)-based silicon oxide film
106
or the like is formed on silicon nitride film
103
to fill trench
104
. Referring then to
FIG. 30
, chemical mechanical polishing (CMP) process or the like is applied to silicon oxide film
106
to leave silicon oxide film
106
only in trench
104
.
Referring then to
FIG. 31
, an aqueous solution of phosphoric acid or the like is used to remove silicon nitride film
103
. Referring then to
FIG. 32
, an aqueous solution of hydrofluoric acid or the like is used to etch silicon oxide film
102
to expose a surface of silicon substrate
101
. Thus an element isolating region A completes.
Referring now to
FIG. 33
, thermal oxidation is used to form a silicon oxide film
107
for forming a gate oxide film on silicon substrate
101
. Referring then to
FIG. 34
, a polysilicon film or the like (not shown) is formed on silicon oxide film
107
. Photolithography and etching are then used to form a gate electrode
109
on silicon substrate
101
with a gate oxide film
107
a
posed therebetween.
A sidewall insulating film
110
is formed on each of both side surfaces of gate electrode
109
. Gate electrode
109
and sidewall insulating film
110
are used as a mask to introduce impurity ions of a predetermined conduction type into a main surface of silicon substrate
101
to form source/drain regions
108
a,
108
b
there. Thus a MOS transistor
112
is formed in an element forming region B. To cover MOS transistor
112
, chemical vapor deposition is used to form a silicon oxide film
111
on silicon substrate
101
.
Thus a main portion of a semiconductor device provided with MOS transistor
112
completes in element forming region B electrically isolated from other regions by element isolating region A
In accordance with the semiconductor device manufacturing method described above, in the
FIG. 28
step a thermal process is performed to form silicon oxide film
105
on a surface of silicon substrate
101
exposed in trench
104
to electrically isolate the silicon substrate
101
surface exposed in trench
104
and a portion in a vicinity thereof that are damaged by the anisotropical etch performed in forming trench
104
.
Furthermore, in the
FIG. 33
step the thermal oxidation or the like used to form silicon oxide film
107
also oxidizes a portion of silicon substrate
101
located at an upper portion in trench
104
.
When silicon oxide film
105
,
107
or the like is grown, however, compressive stress is exerted in silicon substrate
101
substantially parallel to an interface of silicon substrate
101
and the silicon oxide film. The compressive stress is relatively intense particularly at regions S
1
, S
2
shown in
FIG. 35 and a
disadvantageous crystalline defect readily results in silicon substrate
101
at regions S
1
, S
2
.
Thus, when a MOS transistor or the like is formed in element forming region B, the crystalline defect resulting in region S
1
can degrade the reliability of the gate oxide film thereof and current leakage can be caused between the source/drain regions and the silicon substrate. The crystalline defect caused in region S
2
can also reduce the breakdown voltage between adjacent, element forming regions Bs.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the disadvantages described above. One object of the present invention is to provide a semiconductor device reducing a compressive stress caused in a semiconductor substrate in a vicinity of an element isolating trench region to reduce formation of a crystalline defect. Another object of the present invention is to provide a method of manufacturing such a semiconductor device.
A semiconductor device manufacturing method in one aspect of the present invention is that for forming an element isolating trench region electrically isolating an element forming region formed at a main surface of a semiconductor substrate from another element forming region formed at the main surface of the semiconductor substrate, including the steps of forming a trench in a main surface of the semiconductor substrate, and subjecting a surface of the semiconductor substrate located in the trench to a first thermal oxidation process to form a first oxide film and also partially enhancing the thermal oxidation of the semiconductor substrate surface associated with the first thermal oxidation process to provide an uneven interface between the first oxide film and the semiconductor substrate.
In accordance with the manufacturing method, that portion of a surface of a semiconductor substrate located in a trench at which thermal oxidation is enhanced is oxidized more deeply into the semiconductor substrate than other portions are oxidized. Thus the first oxide film formed on the surface of the semiconductor substrate located in the trench has a portion formed relatively deeper as measured from the surface than other portions and the first oxide film and the semiconductor substrate thus have an uneven interface therebetween. A microscopic compressive stress caused in the semiconductor substrate is exerted along the interface of the semiconductor substrate and the first oxide film. Thus when the interface is uneven the microscopic compressive stress will not be directed in one direction. Thus a net compressive stress (or macroscopic compressive stress) caused in the semiconductor substrate is smaller than when the microscopic compressive stress is directed in one direction. This reduces formation of a crystalline defect in regions of the semiconductor substrate at which intensive compressive stress is particularly readily exerted, i.e., regions of the semiconductor substrate near the bottom and opening of the trench.
Preferably the interface forming step of providing the uneven interface includes the steps of forming a layer having a grain boundary on a surface of the semiconductor substrate exposed in the trench, and subjecting the layer having the grain boundary to a first thermal oxidation process.
Thus, oxidation can be promoted more in the portion of the grain boundary of the grain boundary containing layer than in other portions to enhance the oxidation of the portion of the semiconductor substrate located under the grain boundary. Thus, an uneven interface of the first oxide film and the semiconductor substrate can readily be formed.
Still preferably, the grain boundary containing layer is a polycrystalline silicon film having a film thickness of 50 to 500 Å.
With a polycrystalline silicon film having a film thickness of less than 50 Å, it is difficult to partially enhance
McDermott & Will & Emery
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
Vockrodt Jeff
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