Method for fabricating capacitor of semiconductor device

Details Method for fabricating capacitor of semiconductor device Method for fabricating capacitor of semiconductor device

1999-12-30

2001-03-27

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S255000, C438S396000

Reexamination Certificate

active

06207528

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a capacitor of a semiconductor device with greater capacitance by depositing a dielectric layer with a dielectric material, Ta
2
O
5
—Al
2
O
3
with higher structural stability and dielectric constant than a Ta
2
O
5
layer, wherein the Ta
2
O
5
—Al
2
O
3
layer is obtained by adding an aluminum containing compound in the process of depositing a conventional dielectric Ta
2
O
5
layer.
2. Description of the Prior Art
FIG. 1
is a cross-sectional view for illustrating an embodiment of a semiconductor capacitor with a Ta
2
O
5
layer as a dielectric layer in accordance with the prior art.
As shown in
FIG. 1
, a conventional method for fabricating the Ta
2
O
5
capacitor to be used for a semiconductor DRAM device will be described below.
First of all, doped polysilicon is used for forming a bottom electrode
5
, a storage node on a semiconductor substrate, and a Ta
2
O
5
layer
9
is deposited as a dielectric layer on the polysilicon layer
5
by a plasma enhanced chemical vapor deposition (PECVD) method or low pressure CVD (LPCVD) method. In addition, a top electrode (plate electrode)
11
,
13
is deposited with TiN and/or polysilicon, thereby forming a capacitor for a DRAM device.
However, for the process of depositing a dielectric layer, a PECVD method of forming a high quality dielectric layer, and a LPCVD method of forming a dielectric layer with low quality but high step coverage, have been mainly applied for depositing the Ta
2
O
5
layer.
Since the Ta
2
O
5
layer
9
generally has an unstable stoichiometry, some substitution type Ta vacancy atoms inevitably remain in the dielectric layer due to a difference in the composition ratio of Ta and O. Furthermore, in the process of forming the Ta
2
O
5
dielectric layer, an organic material of Ta(OC
2
H
5
)
5
, a precursor of Ta
2
O
5
, and O
2
(or N
2
O) gas are reacted to release and co-exist carbon atoms (C), hydrocarbon (CH
4,
C2H4 etc.) and water (H
2
O)
On the other hand,
FIG. 2
is a schematic view for illustrating internal chemical composition and properties of the Ta
2
O
5
layer shown in FIG.
1
.
As the Ta
2
O
5
layer
9
is shown in the drawing, due to unstable stoichiometry, it remains in a state of Ta
x
O
y
, releasing some substitution type Ta vacancy atoms caused by difference in the composition ratio of Ta and O. Furthermore, an organic material of Ta(OC
2
H
5
)
5
, a precursor of Ta
2
O
5
, and O
2
(or N
2
O) gas are reacted to release and co-exist carbon atoms (C), hydrocarbon (CH
4
, C2H4 etc.) and water (H
2
O) as well.
Therefore, there is a problem in the conventional Ta
2
O
5
capacitor in that the conventional Ta
2
O
5
capacitor increases current leakage and deteriorates dielectric characteristic due to impurities like carbon atoms, ions, radicals remaining in the Ta
2
O
5
dielectric layer, thereby putting a great limitation in application of the Ta
2
O
5
capacitor for a mass production of DRAM devices.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to solve the aforementioned problem and provide a method for fabricating a capacitor of a semiconductor device with greater capacitance by adding an aluminum containing compound in the process of depositing an amorphous Ta
2
O
5
layer in a LPCVD chamber, differently from the conventional method, thereby obtaining a material Ta
2
O
5
—Al
2
O
3
for forming a dielectric layer with higher structural stability and dielectric constant than the Ta
2
O
5
. layer.
In order to accomplish the aforementioned objects of the present invention, there is provided a method for fabricating a capacitor of a semiconductor device comprising the steps of: forming a hemispherical polysilicon layer on a bottom electrode of a storage node; nitrifying the surface of the polysilicon layer for preventing formation of a natural oxide layer on the hemispherical polysilicon layer; forming a Ta
2
O
5
—Al
2
O
3
layer on the surface nitrified polysilicon layer; and forming a plate electrode by depositing metal on the Ta
2
O
5
—Al
2
O
3
layer.
Some principles applied in the process of fabricating a capacitor of the present invention will be described below.
According to the present invention, in the process of depositing the amorphous Ta
2
O
5
through the LPCVD method, a (Ta
2
O
5
)
1−x
—(Al
2
O
3
)
x
(0≦×≦0.5) layer (&egr;=40) with a higher dielectric characteristic can be obtained by adding an aluminum containing compound through a surface chemical reaction. Furthermore, the Ta
2
O
5
—Al
2
O
3
layer has a structural stability because there are covalent bonds between a perovskite type structure of Al
2
O
3
and Ta
2
O
5
in the resultant dielectric layer.
On the other hand, due to unstable chemical stoichiometry of the Ta
2
O
5
layer, there may partially be oxygen vacancy state of substitution type Ta atoms. However, the number of oxygen vacancies in the aforementioned Ta
2
O
5
—Al
2
O
3
layer may be varied depending on the quantity and bonding state of Al
2
O
3
compound, but it is smaller than the pure form of the Ta
2
O
5
layer. As a result, the Ta
2
O
5
—Al
2
O
3
capacitor is relatively smaller in the level of current leakage than Ta
2
O
5
capacitor.


REFERENCES:
patent: 3949275 (1976-04-01), Muenz
patent: 4670355 (1987-06-01), Matsudaira
patent: 5134086 (1992-07-01), Ahn
patent: 5486488 (1996-01-01), Kamiyama
patent: 5741734 (1998-04-01), Lee
patent: 6136641 (2000-10-01), Won et al.
Fazan et al., A High-C Capacitor with Ultrathin CVD—Ta2O5 Films Deposited on Rugged Poly-Si for High Density DRAMs, IEDM Technical Digest, 1992, pp. 263-266.*
Kamiyama et al., Ultra-Thin TiN/Ta2O5/W Capacitor Technology for 1Gbit DRAM, IEDM Technical Digest, 1993, pp. 49-52.*
Tang et al., Trends in DRAM Dielectrics, IEEE Circuits and Devices Magazine, 13 (May 1997) 27-34.*
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Banerjee et al., Fabrication and Performance of Selective HSG Storage Cells for 256 Mb and 1 Gb RAM Applications, IEEE Transactions on Electron Devices, 47 (Mar. 2000) 584-592.*
Ha et al., A Cost Effective Embedded DRAM Integration for High Density Memory and High Performance Logic Using 0.15 Micron Technology Node and Beyond, IEEE Transactions on Electron Devices, 47 (Jul. 2000) 1499-1506.

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