Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
1998-04-15
2001-05-08
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S002000, C331S016000, C331S018000, C331S025000, C327S147000, C327S156000, C375S376000, C455S260000
Reexamination Certificate
active
06229399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a multiband PLL frequency synthesizer for generating a frequency signal over a plurality of bands.
2. Description of the Prior Art
A multiband PLL frequency synthesizer for generating a frequency signal over a plurality of bands is known.
FIG. 7
is a block diagram of a prior art multiband PLL (phase-locked loop) frequency synthesizer. This prior art multiband PLL frequency synthesizer includes three PLL frequency synthesizing circuits
313
,
314
, and
315
. The PLL frequency synthesizing circuits
313
,
314
, and
315
generate frequency signals at different bands respectively.
FIG. 8
is an illustration of the prior art showing an example of using the prior art multiband PLL frequency synthesizer shown in FIG.
7
. In FIG.
8
. the PLL frequency synthesizing circuits
313
,
314
, and
315
generate frequency signals at bands f
1
to f
2
, f
3
to f
4
, and f
5
to f
6
respectively. A switch
316
outputs one of the frequency signals from the PLL frequency synthesizing circuits
313
,
314
, and
315
.
In this circuit, there are many parts used because three similar circuits are used.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a superior multiband PLL frequency synthesizer.
According to the present invention there is provided a first PLL frequency synthesizer which includes: a reference signal generation circuit for generating a reference signal of which frequency is controlled in accordance with a reference frequency control signal; a phase comparing circuit for phase-comparing a frequency-divided signal with the frequency reference signal to output a phase difference signal; a low-pass filter circuit for low-pass-filtering the phase difference signal with one of a plurality of cut-off frequencies selected in response to the filter control signal; a voltage controlled oscillation circuit for generating and outputting an oscillation signal in accordance with an output of the low-pass filter circuit; a frequency dividing circuit for frequency-dividing the oscillation signal and supplying the frequency-divided signal to the phase comparing circuit; and a control circuit for generating the reference frequency control signal and the filter control signal in accordance with a frequency command signal.
In the first PLL frequency synthesizer, the frequency dividing circuit frequency-divides the oscillation signal in first and second modes in accordance with a frequency dividing control signal, the frequency dividing circuit frequency-dividing the oscillation signal by an integer in the first mode and frequency-dividing the oscillation signal in the second mode such that the oscillation signal is divided by a fraction using control data, the control circuit further generating the frequency dividing control signal, the integer, and control data in accordance with the frequency command signal. In this case, the frequency dividing circuit includes a frequency divider supplied with the integer and a dividing control circuit for controlling the frequency divider in the second mode such that the integer is periodically varied in accordance with the frequency dividing control signal.
In the first PLL frequency synthesizer, the low-pass filter circuit comprises a loop filter for charging and discharging a constant current for a phase difference interval represented by the phase difference signal and a switch controlled in response the filter control signal, one terminal of the switch being supplied with the phase difference signal, and a filter circuit including a first capacitor of which one terminal is connected the other terminal of the switch, the other terminal of the first capacitor being connected to the ground, and a series circuit including a resistor and a second capacitor, one end of the series circuit being connected to the other terminal of the switch and the other end of the series circuit being connected to the ground.
In the first PLL frequency synthesizer, the voltage controlled oscillation circuit includes a plurality of oscillation circuits, the oscillation signal is outputted by one of a plurality of the oscillation circuits in accordance with an oscillation control signal, the control circuit further generating the oscillation control signal in accordance with the frequency command signal.
According to the present invention there is provided a second PLL frequency synthesizer which includes: a reference signal generation circuit for generating a reference signal of which frequency is controlled in accordance with a reference frequency control signal; a phase comparing circuit for phase-comparing a frequency-divided signal with the frequency reference signal to output a phase difference signal; a low-pass filter circuit for low-pass-filtering the phase difference signal; a voltage controlled oscillation circuit for generating and outputting an oscillation signal in accordance with an output of the low-pass filter circuit; a frequency dividing circuit for frequency-dividing the oscillation signal in first and second modes in accordance with a frequency dividing control signal, the frequency dividing circuit frequency-dividing the oscillation signal by an integer in the first mode and frequency-dividing the oscillation signal in the second mode such that the oscillation signal is divided by a fraction, and supplying the frequency-divided signal to the phase comparing circuit; and a control circuit for generating the reference frequency control signal and the frequency dividing control signal in accordance with a frequency command signal.
In the second PLL frequency synthesizer, the frequency dividing circuit includes a frequency divider supplied with the integer and a dividing control circuit for controlling the frequency divider in the second mode such that the integer is periodically varied in accordance with the frequency dividing control signal.
In the second PLL frequency synthesizer, the low-pass-filtering circuit low-pass-filters the phase difference signal with one of a plurality of cut-off frequencies selected in response to a filter control signal and the control circuit further generates the filter control signal in accordance with the frequency command signal. In this case, the low-pass filter circuit includes a loop filter for charging and discharging a constant current for a phase difference interval represented by the phase difference signal and a switch controlled in response to the filter control signal, one terminal of the switch being supplied with the phase difference signal, and a filter circuit including a first capacitor of which one terminal is connected to the other terminal of the switch, the other terminal of the first capacitor being connected to the ground, and a series circuit including a resistor and a second capacitor, one end of the series circuit being connected to the other terminal of the switch and the other end of the series circuit being connected to the ground.
In the second PLL frequency synthesizer, the voltage controlled oscillation circuit includes a plurality of oscillation circuits, the oscillation signal is outputted by one of a plurality of the oscillation circuits selected in accordance with an oscillation control signal, the control circuit further generating the oscillation control signal in accordance with the frequency command signal.
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patent: 3710274 (1973-01-01), Basse et al.
patent: 3729688 (1973-04-01), Cerny, Jr. et al.
patent: 4510461 (1985-04-01), Dickes et al.
patent: 4629999 (1986-12-01), Hatch et al.
patent: 4862296 (1989-08-01), Murabayashi
patent: 5420545 (1995-05-01), Davis et al.
patent: 5471661 (1995-11-01), Atkinson
patent: 5576666 (1996-11-01), Rauvola
patent: 5675292 (1997-10-01), McCune, Jr.
patent: 5686864 (1997-11-01), Martin et al.
patent: 5729179 (1998-03-01), Sumi
patent: 6284037 (1994-10-01), None
Adachi Hisashi
Kato Hidenobu
Tobise Daisuke
Connolly Bove Lodge & Hutz
Matsushita Electric - Industrial Co., Ltd.
Mis David
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