Delay equalization apparatus and method

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

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Details

327157, 327158, 327148, 327149, 327244, 331 1A, H03K 513, H03K 500

Patent

active

058252266

ABSTRACT:
A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.

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