Cleaning and liquid contact with solids – Processes – Including application of electrical radiant or wave energy...
Reexamination Certificate
1998-03-17
2001-03-13
El-Arini, Zeinab (Department: 1746)
Cleaning and liquid contact with solids
Processes
Including application of electrical radiant or wave energy...
C134S001200, C134S002000, C134S019000, C134S032000, C134S902000, C438S714000
Reexamination Certificate
active
06199561
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an improvement applicable to a method for ashing and to an apparatus employable for ashing. More specifically, this invention relates to an improvement applicable to a method for ashing and an apparatus employable for an ashing process conducted employing plasma to remove a resist layer which was employed as a mask employable for an ion implantation process.
BACKGROUND OF THE INVENTION
A photo lithography process is one of the important tools employable for producing a semiconductor device. The photo lithography process consists of a step to spin coat a photo resist to produce a photo resist layer on a semiconductor substrate or layer, a step to expose a selected area of the photo resist layer, a step to develop the exposed photo resist layer to produce a photo resist pattern, a step to etch a selected portion of the semiconductor substrate or layer which selected portion is unconcealed by the photo resist pattern, and a step to remove the photo resist pattern which was employed as the etching mask in the previous etching step. The former half of the photo lithography process can be employed to produce a mask employable for an ion implantation process. In other words, a resist pattern produced by selective exposure of a resist layer can be employed as a mask for an ion implantation process employable for introducing impurities in the surface region of a semiconductor substrate or layer. An ashing process conducted employing oxygen radicals or oxygen plasma containing oxygen ions, is usually employed to remove the resist pattern, after an ion implantation process is finished employing the resist pattern as a mask. Since the ashing rate of such an ashing process is accelerated by temperature, it is preferable to conduct such an ashing process under a high temperature.
An ion implantation process conducted employing a resist pattern as a mask is accompanied by a phenomenon to reform the chemical composition of the substance of the top surface of the resist pattern. In other words, the top surface of the resist pattern is converted to a hardened layer, during an ion implantation process.
When a semiconductor substrate or layer selectively covered by a resist pattern of which the top surface has been converted to a hardened layer, is heated up to a high temperature e.g. 150° C. or higher in an ashing apparatus for the purpose to remove the resist pattern, the hardened layer is broken by a high pressure caused by expansion of an evaporated substance located under the hardened layer. This explosive destruction of the hardened layer covering a resist pattern is called popping phenomenon. The popping phenomenon causes dispersion of resist particles, further causing contamination of the surface of the semiconductor substrate or layer and contamination of the internal surface of the ashing apparatus.
An ashing process conducted employing plasma under a low temperature for the purpose to remove an exposed resist pattern covered by a hardened layer, while avoiding popping phenomenon, is readily accompanied by a less ashing rate, resulting in a less magnitude of throughput.
Accordingly, a long standing requirement in this technical field is development of an ashing process for removing a resist pattern which was employed as a mask for an ion implantation process and is covered by a hardened layer and an apparatus employable therefor, both of which are free from popping phenomenon.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, the object of this invention is to provide a method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted, the ashing process being free from popping phenomenon, and to provide an apparatus employable for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted, the ashing apparatus enabling an ashing process free from popping phenomenon.
To achieve the first one of the foregoing objects, a method for ashing a resist pattern covered by a hardened layer in accordance with a first embodiment of this invention comprises: a first step for conducting an ashing process at a first temperature at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature at which the ashing rate is high, for removing the resist pattern.
In the foregoing method for ashing a resist pattern covered by a hardened layer, the first temperature is preferably 120° C. or less and the second temperature is preferably 150° C. or higher.
To achieve the second one of the foregoing objects, an apparatus employable for ashing a resist pattern covered by a hardened layer in accordance with a second embodiment of this invention comprises: a reaction chamber having a gas inlet for charging a gas into the reaction chamber, a gas outlet for discharging the gas from the reaction chamber and a means for activating the gas to convert the same to a mixture of plasma, radicals and ions, a semiconductor wafer supporter for supporting a semiconductor wafer, the semiconductor wafer supporter being movable in the vertical direction and being able to stay at three independent levels, a circular stage having a surface parallel to the semiconductor wafer supporter and being kept at a predetermined temperature, and a means for moving the semiconductor wafer supporter in the vertical direction and for keeping the semiconductor wafer supporter at the three independent levels.
Derived from an apparatus employable for ashing a resist pattern covered by a hardened layer in accordance with the second embodiment of this invention is an apparatus employable for ashing a resist pattern covered by a hardened layer in accordance with a modification of the second embodiment of this invention, wherein an annular stage movable in the vertical direction is arranged surrounding the circular stage, for the purpose to allow three independent heating positions for the semiconductor wafer supported by the semiconductor wafer supporter.
To achieve the second one of the foregoing objects, an apparatus employable for ashing a resist pattern covered by a hardened layer in accordance with a fourth embodiment of this invention comprises: a reaction chamber having a gas inlet for charging a gas into the reaction chamber, a gas outlet for discharging the gas from the reaction chamber and a means for activating the gas to convert the same to a mixture of radicals and ions, a heating means for heating a semiconductor wafer, the heating means being arranged in a position to face the semiconductor wafer, a semiconductor wafer supporter means for supporting the semiconductor wafer and for changing the mutual distance between the semiconductor wafer supporter means and the semiconductor wafer and a shutter means to intervene between the heating means and the semiconductor wafer.
In the apparatus for ashing a resist pattern covered by a hardened layer in accordance with the third embodiment of this invention, the heating means can be a lump.
REFERENCES:
patent: 5478403 (1995-12-01), Shinagawa et al.
Shuzo Fujimura et al., “Ashing of Ion-Implanted Resist Layer”, Proc. of 1989 Intern. Symp. on MicroProcess Conference pp. 227-233.
El-Arini Zeinab
Jones Volentine, LLC
OKI Electric Industry Co., Ltd.
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