Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-12-12
2001-09-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185240, C365S185280, C365S185050
Reexamination Certificate
active
06288936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory for storing multivalue data, and more particularly to a semiconductor nonvolatile memory with a read buffer circuit that can read multivalue data stored in memory cells using a simple configuration.
2. Description of the Related Art
Semiconductor nonvolatile memory, such as flash memory, consists of cell transistors having floating gates in the channel area that lies between the source and drain areas. Injection of an electrical charge into these floating gates causes a change in the threshold voltage of the cell transistors and thus records data. The recorded data is read using the difference between the threshold values of the cell transistors.
In a conventional nonvolatile memory, one-bit data is recorded using the state in which electrical charges are not accumulated in the floating gates (state in which the threshold voltage is low when the charge is an electron) and the state in which electrical charges are accumulated (state in which the threshold voltage is high when the charge is an electron). The state in which electrons are not accumulated in the floating gates is a state of data
1
recorded or a deleted state. Accumulation of electrons in the floating gates indicates a state in which data
0
has been recorded or a programming state.
Because semiconductor nonvolatile memory, such as flash memory, is small and stores data even when the power is turned off, it is widely used as an image and audio recording medium in equipment such as digital cameras. Greater storage capacity is being demanded but, as described above, in a conventional nonvolatile memory for normal use a cell transistor can only store one-bit (single value) data.
For this reason, the recording of multivalue data, such as 2 bits data, in cell transistors is being proposed. By controlling the electrical charge injected into floating gates, a plurality of threshold voltage states is achieved and multivalue data can be recorded. For example, when 4 value data (2 bits) is stored four threshold voltage states will be stored.
However, to read 2 bits data from a cell transistor, it is necessary to read the first bit of data and then read the second bit of data. Accordingly, a latch circuit that temporarily holds the two bits of data is required in the read buffer circuit for reading data recorded in the cell transistor.
Generally, a read buffer circuit is installed for each bit line and so it is necessary to simplify the read buffer circuit configuration as much as possible. However, as described above, with the plurality of data values stored in a cell transistor, when a plurality of latch circuits is installed in a read buffer circuit, the scale of the read buffer circuit increases and, from the point of view of integration, goes against the demand for greater capacity.
Furthermore, when programming (writing) multivalue cell transistors, a plurality of bits must be input and an electrical charge that corresponds to these bits must be injected into the floating gates. Here, it is preferable that the programming operation corresponding to the relationship between the plurality of bits and the multiple values is realized using a simple program circuit.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a read buffer circuit having a relatively simple configuration in nonvolatile memory for recording multivalue data.
A further object of the present invention is to provide a circuit with a simple configuration that enables programming of multivalue data in nonvolatile memory for recording multivalue data.
To achieve the above objects, according to the first aspect of the present invention, a nonvolatile memory that has a plurality of floating gate type cell transistors comprises a read buffer circuit, connected to the bit line, that detects the threshold voltage states in the cell transistor. Each cell transistor can hold 2
N
threshold voltage states and accordingly, the read buffer circuit reads N bits of data. For this purpose, the read buffer circuit has a latch circuit that latches the read data in accordance with the detected threshold voltage state. This latch circuit has a first and second latch reversal circuit for reversing the latched state to the first or second state.
When the read buffer circuit reads the first bit being held in the cell transistor, the latch circuit in its initial state is reversed or not reversed by the first latch reversal circuit in accordance with the detected first and second threshold voltage state, or third and fourth threshold voltage state, and that latch state is output as the first data. Furthermore, when the lower order second bit held in the cell transistor is read next, the read. buffer circuit is reversed or not reversed from the latch state corresponding to the first data above by the first latch reversal circuit in accordance with the detected first or second threshold voltage state. Then, it is reversed or not reversed by the second latch reversal circuit in accordance with the detected third or fourth threshold voltage state and the latch state is output as the second data.
The above operations enable the read buffer circuit to differentiate between and latch at least two bits of data in the one latch circuit. In other words, after the latch circuit is reset to its initial state, the first data is held then output and the second data is held then output sequentially.
In the second aspect of the present invention, nonvolatile memory having a plurality of floating gate type cell transistors comprises a program input circuit that, in response to the input of the first bit and then the lower order second bit, outputs program data showing whether or not a program exists, and a read buffer circuit, connected to the bit line, for detecting the threshold voltage state of the cell transistors. During the programming, the read buffer circuit latches the above program data and sends the program data to the bit lines. Furthermore, the above program input circuit outputs the above program data in accordance with the combination of the first and second bits in the first cycle which programs from the first state (the deleted state) to second state, in the second cycle which programs from the first to the third state, and in the third cycle which programs from the first to the fourth state.
Provision of the above program input circuit enables program data to be held in the latch circuit within the read buffer circuit in accordance with the two bit combination. Accordingly, the cell transistors can be programmed in accordance with the program data held in the latch circuit.
REFERENCES:
patent: 6067248 (2000-05-01), Yoo
patent: 404184794A (1992-07-01), None
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Lam David
Nelms David
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