Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-07-12
2001-06-05
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S152000, C341S166000, C341S138000
Reexamination Certificate
active
06243033
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method and system for representing a signal value. More particularly, it relates to a signal value representing method aimed at enhancing the dynamic range and improving the precision.
DESCRIPTION OF THE RELATED ART
In representing the signal value, a broad dynamic range (range of the values that can be represented) and a high precision in the signal value are generally required. In keeping up with the recent tendency towards finer design rule in the semiconductor devices, it is desired to reduce the power source voltage of the semiconductor device to improve the reliability and to reduce power consumption of the device.
In the conventional representation of analog signal values, there are an analog signal value representing system and a digital signal representing system.
In the analog signal representing system, one signal line is used for transmission, with the signal value being represented by the potential level between a first power source level and the second power source level. The signal value can be continuously represented by a level between the first power source level and the second power source level. Therefore, the dynamic range is proportionate to the difference between the first power source level and the second power source level.
The digital signal value representing method is realized using N signal lines, with the potential level of the signal line being the first power source level or the second power source level. In this case, the signal level can be represented in 2{circumflex over ( )}N, where {circumflex over ( )} denotes the power. Therefore, the dynamic range is 2{circumflex over ( )}N.
SUMMARY OF THE DISCLOSURE
The following problems have been encountered in the course of the investigations toward the present invention.
With the present analog signal value representing system, the dynamic range is lowered with the lowering of the power source voltage. Simultaneously, the signal precision is deteriorated. This deterioration in signal precision may possibly be accounted for as follows:
If, for example, a signal having delay time ranging from 0 ns (nanosecond) to 100 ns is represented by the power source voltage of 5 V, with the dynamic range being 5 V, that is if the time is represented by voltage by linear conversion, the time of 20 ns can be represented by the voltage of 1 V.
If the power source voltage is reduced to 1V, the dynamic range is 1, such that 1 V needs to be represented by 100 ns.
If the noise of, for example, 100 mV is induced in the signal value with the power source voltage of 5 V, there is produced an error of 2 ns in the delay time. If, with the power source voltage of 1 V, the noise of 100 mV is induced in the signal value, the error amounts to 10 ns.
If the noise is induced in the signal value, the low power source voltage is subjected to and affected by a larger noise, that is, deteriorated in precision.
The digital signal value representing method is not affected by the lowering of the power source voltage. However, the precision, that is resolution, depends on the number N of the signal lines, and is proportionate to ½{circumflex over ( )}N. That is, if the number of signal lines is increased, the precision is increased, however, the increased number of the signal lines leads to the increased area of the apparatus. That is, the digital signal value representing method has the problem that, if the number of signal lines used is small, the precision is correspondingly lowered.
In view of the above-mentioned problem of the prior art, it is an object of the present invention to provide a signal value representing method or system having a wide dynamic range and high precision at a low power source voltage.
According to an aspect of the present invention, there is provided a signal value representing method which resides in the combination of analog signal value representation and digital signal value representation. In a second aspect, the signal representation is by M+1 signal lines, of which M signal lines are used for the digital signal value representation and the remaining one signal line is used for analog signal value representation. In a third aspect, the signal value represented by the analog signal value representation is set so as to be equal to the smallest value of the digital signal value representing method.
According to a fourth aspect there is provided a signal value representing system comprising: M digital signal input lines where M is positive integer and an analog signal input line, and a synthesizing unit combining M digital input signals input from the M digital signal input lines and an analog signal to output a synthesized signal wherein the synthesized signal is represented by the combination of a digital signal value representation supplied by the M digital signal input lines and an analog signal value representation supplied by the sole analog signal input line. The digital input signal represented by the digital signal value representation by the M digital signal input lines is set to have an interval of discrete values, of the same value as a size represented by the analog signal value representation supplied by the sole analog signal input line.
The digital signal value representation is formed of a plurality of discrete value signals under a weighted representation of signal, and the analog signal value representation is formed of a sole continuous value signal.
The continuous value signal is of a value associated with the smallest resolution represented by said discrete value signals.
The synthesized signal can be output as a signal value of voltage, current, frequency or delay time.
According to a fifth aspect of the invention, there is provided a signal value representing system comprising: means for inputting a plurality of discrete value signals under a weighting representation of a signal with a pre-set resolution, means for inputting a sole continuous-valued signal, means for synthesizing a sole signal value by combining the discrete value signals and the sole continuous-valued signal to output the sole signal value.
The sole continuous-valued signal corresponds to the smallest resolution given by the discrete-valued signals.
According to a sixth aspect of the present invention there is provided a signal synthesizing system comprising: a sole analog input line to supply a sole analog signal, a plurality of input lines supplying discrete signals from each other, and a synthesizing unit which combines the sole analog signal and the discrete signals to output a synthesized signal, wherein said sole analog signal is selectively combined with at least one of the discrete signals.
The synthesizing unit comprises a series of switching elements, one receiving the sole analog signal and each of the rest of the switching elements receiving one of the discrete signals, respectively, and the switching elements have a common output to provide the synthesized signal.
The switching elements comprise transistors.
The transistors comprises FETs having a common output to provide the synthesized signal.
The common output further comprises a current mirror circuit to provide a current output.
The synthesizing unit comprises a delay time varying unit and a selection unit, the delayed time varying unit receiving an input signal and delaying time in accordance with the sole analog signal to output a delayed signal, the selection unit receiving the discrete signals, and wherein the selection unit selectively receives the delayed signal from the delay time varying unit to synthesize a delayed signal representing a discrete delay time having a modified delay time with the sole analog signal.
The delay time unit comprises a plurality of tandem-arrayed delaying elements, each being selectable or switchable by the selection unit according to the discrete signals, each of the delaying elements being controlled by the sole analog signal.
One output of the delaying elements is selected by the selection unit, delay time of the output being controlled by the sol
NEC Corporation
Tan Vibol
Tokar Michael
Young & Thompson
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