Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-29
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185220
Reexamination Certificate
active
06292394
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for programming of semiconductor memory cells in general, and particularly, to methods for programming to any threshold level.
BACKGROUND OF THE INVENTION
A typical method for programming a nonvolatile semiconductor memory cell, such as a nitride, read only memory cell (NROM), involves initially applying a programming pulse thereto, thus causing charge to become trapped in a retention layer of the cell. This trapped charge induces the threshold voltage V
TH
of the cell to increase.
Ordinarily, the programming pulse is followed by a program verify pulse. Via various known in the art methods, the program verify pulse verifies the programmed level of the cell. In memory cells such as the NROM, this is accomplished via a reverse read action. If the program verify pulse reveals that the cell has not yet reach the programmed level, an additional programming pulse is applied, followed by a subsequent program verify pulse. Typically, during the programming process, the programming pulses increase in voltage level, commencing at a relatively low voltage level and terminating at a higher level voltage. An example of such is described in Applicant's co-pending U.S. patent application Ser. No. 09/563,923 Programming Of Nonvolatile Memory Cells, filed on May 4, 2000 and incorporated herein by reference.
When the cell passes program verify, the cell is considered “programmed”, and the programming process is terminated. If however, due to noise, charge leakage and the like, the program verify pulse of a programmed cell does not accurately verify the programmed state of the cell, further programming may induce too much charge into the retention layer, and cause a condition known as over-programming. In applications such as NROM, it is important to prevent over-programming of the cell. Over-programming of the cell creates a broad pocket of trapped charge, which reduces the longevity of the cell.
Conversely, if the cell is under-programmed, the threshold voltage V
TH
of the cell will not be high enough to read as programmed. Thus, inaccurate programming/verifying methods result in cell program mis-readings, and subsequent cell mis-programming.
The opposite procedure of programming is usually referred to as “erase”. For electrically erasable programmable read only memory (EEPROM) cells, erasure changes the threshold voltage in the opposite direction to that of programming. It is equally important to prevent over-erasure (as over-programming), so as to avoid excessive reduction of the threshold voltage and subsequent deterioration in the quality of the cell's composition.
U.S. Pat. No. 5,523,972 discusses a programming method wherein each cell is queried for program verification. Those cells that pass verification are marked as programmed and are not queried again. Hence, since the method does not teach repeat queries, cells that have slipped below the programmed voltage threshold V
TH
are not discovered.
Alternatively, U.S. Pat. No. 5,172,338 discusses repeated query of the cells. Each cell that does not pass program verify, either on a previous query or on a subsequent query, receives a program pulse. However, for those cells which pass a previous program verify, yet failed a subsequent verify, it is risky to apply program pulses, since the continuance of programming subjects those cells to the possibility of over-programming.
It is thus important to devise an accurate method that supports generally precise programming of cells to a level that insures a reliability margin.
SUMMARY OF THE PRESENT INVENTION
It is an object of the present invention to provide a method for programming of the threshold voltage of a semiconductor memory cells. In embodiments of the present invention, the programming methods described herein are applicable to both programming and erasure.
There is therefore provided in accordance with a preferred embodiment of the present invention, a method for programming an array having a multiplicity of memory cells. The method includes, per cell to be programmed, verifying a programmed or non-programmed state of the cell and flagging those of the cells that verify as non-programmed during one of the verify steps after having previously verified as programmed. A programming pulse having a programming level is applied to the non-programmed cells which are not flagged cells. The steps of verifying, flagging and applying are then repeated until all of the cells verify as programmed at least once. Subsequently, a boost pulse having a boost programming level lower than the programming level is applied to the flagged cells.
Alternatively, the step of repeating includes increasing the programming level of the programming pulse. The programming level may be increased by between 0.05 to 0.3 volts. External means may be used to determine the increase, which may be either constant or variable voltage increases. The programming pulses may also vary in length of time.
The first step of applying includes the step of applying a programming pulse to a gate, a drain, or a source of the non-programmed cells which are not flagged cells.
The step of verifying may include determining a verifying level by external means, where the verifying level may be a constant voltage level or a variable voltage level. The step of verifying may also include verifying whether a threshold voltage of a cell is below a determined level.
There is therefore provided in accordance with an alternative preferred embodiment of the present invention, a method for erasing an array having a multiplicity of memory cells. The method includes the steps of, per cell to be erased, verifying an erased or non-erased state of the cell and flagging those of the cells that verify as non-erased during one of the verify steps after having previously verified as erased. An erasing pulse having an erasure level is applied to the non-erased cells which are not flagged cells. The steps of verifying, flagging and applying are repeated until all of the cells have verified as the erased at least once. Subsequently, a boost pulse having a boost erase level lower than the erased level is applied to the flagged cells.
The step of repeating includes increasing the erasure level of the erasing pulse, sometimes by between 0.05 to 0.3 volts. The erasure level may be determined by external means and may be increased by constant voltage steps or by variable voltage steps. The erasure pulses may vary in length of time.
The first step of applying includes applying a programming pulse to a gate, a drain, or a source of the non-programmed cells which are not flagged cells. The step of verifying includes verifying whether a threshold voltage of a cell is above a determined level.
There is therefore provided in accordance with an alternative preferred embodiment of the present invention, a method for programming an array having a multiplicity of memory cells. The method includes the steps of, per cell to be programmed, verifying a coarse programmed or non-programmed state of the cell and flagging those of the cells that verify as non-programmed during one of the verify steps after having previously verified as programmed. A coarse programming pulse having a coarse programming level is applied to the non-programmed cells which are not flagged cells.
The steps of verifying, flagging and applying are repeated until all of the cells verify as programmed at least once. A fine programming pulse is then applied to the flagged cells. Next, a complete programmed state or a complete non-programmed state of the cell is verified and the second steps of verifying and applying are repeated until all of the cells are very as fully programmed at least once.
The first step of verifying includes verifying a cell threshold voltage to a level that is within &agr; volts of a desired threshold voltage. Sometimes &agr; is in the range of 0.2-0.5 volt, where &agr; is the maximum change in threshold voltage that can be induced in a cell with a coarse programming pulse.
The second step of verifying may also in
Cohen Zeev
Eitan Boaz
Maayan Eduardo
Eitan Pearl Latzer & Cohen-Zedek
Lam David
Nelms David
Saifun Semiconductors Ltd.
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