Semiconductor memory with built-in cache

Details Semiconductor memory with built-in cache Semiconductor memory with built-in cache

1999-12-10

2001-06-19

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S230090

Reexamination Certificate

active

06249450

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device such as a dynamic random-access memory (DRAM), more particularly to a semiconductor memory device with a built-in cache in which data can be stored for quick recall.
A DRAM has, among other circuits, an array of memory cells identified by row and column addresses, and a row of sense amplifiers. In read or write access, a row address is input, the memory cells in the addressed row are coupled to the sense amplifiers, and their data are amplified. Next a column address is input, and in read access for example, the amplified data for the addressed column are output to a data bus. Further column addresses may then be input to access the data of other columns in the same row. When such access ends, in a conventional DRAM, the sense amplifiers are disabled, and the data remain held only in the memory cell array.
A problem in the conventional DRAM is that before each access cycle, the sense amplifiers, and the bit lines that couple them to the memory cells, must be precharged by equalizing them to a certain potential. Furthermore, at the beginning of every cycle, the sense amplifiers must amplify the data in an entire row of memory cells. Substantial time is required for these operations, particularly in a large-scale memory with long bit lines, which have large intrinsic capacitances that must be charged and discharged. This severely limits the access speed of the device.
One possible solution to this problem is to retain data in the sense amplifiers by leaving them enabled at the end of an access cycle, thereby using the sense amplifiers as a cache. Then if the same row address is input again, the addressed data are immediately available from the sense amplifiers and do not have to be read from the memory cells. This scheme is particularly suited to a device in which the memory cell array is divided into multiple banks, and multiple rows of sense amplifiers are provided, permitting data from different banks to be cached in different sense amplifier rows.
The utility of this method is restricted, however, by the need to refresh data in DRAM memory cells periodically. Each time a refresh is carried out, the data being held in the relevant sense amplifiers are lost. The data are also lost if the device is placed in standby and the sense amplifiers are powered down.
Another problem is that each row of sense amplifiers can hold data for only a single row of memory cells. If access alternates between two rows in the same bank, for example, the above method confers no benefit.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to enable rapid access to data in a semiconductor memory device.
Another object of the invention is to avoid loss of rapidly accessible data when a refresh occurs.
Yet another object is to enable refresh cycles and access cycles to take place simultaneously.
Still another object is to reduce current dissipation when data are transferred from memory cells to sense amplifiers.
The invented semiconductor memory device has a row-column array of memory cells for storing data. Bit lines extending in the column direction transport data to and from memory cells selected by word lines extending in the row direction. The bit lines are coupled via a row of first switching elements to corresponding sense lines, to which sense amplifiers are coupled.
According to a first aspect of the invention, one or more rows of cache cells are coupled to the sense lines.
According to a second aspect of the invention, column data lines are coupled via second switching elements to the sense lines, and one or more rows of cache cells are coupled to the column data lines.
In either aspect of the invention, each row of cache cells can store data from an arbitrary row of memory cells. Data transferred from the memory cells to the sense lines and amplified by the sense amplifiers can be placed in the cache cells for quick recall later. The cache cells can continue to store such data while the sense amplifiers are refreshing the memory cells.
If the cache cells are coupled to column data lines, then during refresh operations, the column data lines can be disconnected from the sense lines, and access to data on the column data lines can continue while the refresh is in progress.
A tag circuit is provided to keep track of the row addresses of the memory cells having data stored in the cache cells, and control transfers of data to and from the cache cells.


REFERENCES:
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patent: 5184320 (1993-02-01), Dye
patent: 5226009 (1993-07-01), Arimoto
patent: 5226147 (1993-07-01), Fujishima
patent: 5249282 (1993-09-01), Segers
patent: 0 499 256 A1 (1992-08-01), None
patent: 0 552 667 A1 (1993-07-01), None
IEEE International Solid State Circuits Conference, vol. 35, Feb. 1, 1992, pp. 148-149, 269.

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