Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Reexamination Certificate
1998-12-22
2001-05-29
Etienne, Ario (Department: 2155)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
C709S233000, C709S234000, C709S235000, C710S039000, C710S060000
Reexamination Certificate
active
06240458
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to data transfer request management in data processing systems, and more particularly to an interface and programmable interface control system and method for selectively providing, and controlling the rate of, data transfer requests to destination resources, thereby providing the ability to manipulate data throughput under normal operating conditions, and to provide a means for performing transaction processing testing.
BACKGROUND OF THE INVENTION
Data processing systems generally include multiple units such as processing units, memory units, input/output units, and the like, which are interconnected over one or more system interfaces. The interfaces provide for the transfer of digital signals between the units. Since many of the operations within data processing systems involve such transfers, the efficiency of the interfaces has a major impact on the overall performance of the data processing system.
Many conventional interfaces used within data processing systems have several types of signal lines, including data lines for transferring data signals, and address lines for transferring address signals. The address lines generally provide information indicative of the type of request, and further indicate a unit and/or a particular addressable resource associated within the unit that is involved with the request. The data lines provide data signals which are associated with the request.
Requests for data transfers may occur at a faster rate than the memory and associated cache coherency logic can sustain. A buffering technique may be used to queue such requests until they can be processed. However, the queuing function can sometimes result in inefficient and discriminatory request servicing. In some cases, one processor's requests may be repeatedly processed, while another's are left relatively unattended. In other cases, a processor having relatively few requests may needlessly tie up system resources by receiving unnecessary request service polls. These situations can reduce available request bandpass, and increase the probability of request stalling or request lockout. To address this issue, the buffering technique may include a priority scheme to output the data transfer requests according to a priority assigned to each of the data transfer requests. One priority scheme known in the art is known as a “fixed” request priority scheme. Each requester is assigned a fixed priority value, and requests are handled according to this associated priority value. Those requests having a high fixed priority value are always handled prior to those having relatively low priority values. Another request priority scheme is referred to as “snap-fixed”, where input request activity is continually or periodically polled. This results in a captured “snapshot” of the request activity at a given time. All of the captured requests are processed in a fixed order until all requests in the snapshot have been processed, at which time a new snapshot is taken. A “simple rotational” priority scheme involves changing the requester priority on a periodic basis. For example, the requester priority may be changed whenever a request is granted priority. Requester (N−1) moves to priority level (N), requester (N) moves to (N+1), and so forth.
Regardless of the priority scheme used, there may be times when the implemented priority scheme inhibits execution of a desired system operation. For example, testing of a complex multiprocessing system having multiple data transfer sources and multiple data transfer destinations can be incredibly complicated, particularly where test programs must be written to simulate transaction “stress” situations. Such a transaction stress situation may occur during normal operation where some resources, like memory, are suddenly inundated with pending data transfer requests. When this occurs, memory response times may be reduced, causing the data transaction queues to fill. The requesting modules must be able to accommodate this situation to avoid queue overrun problems, and it is therefore important to be able to simulate and test these conditions. Further, the memory resources must be able to manage and absorb the high volume of sudden request traffic and properly respond to the requesting modules. Again, these situations require thorough testing.
In order to prepare test programs to simulate these stress conditions, a detailed knowledge of the entire hardware implementation would be required in order to predict the direct effect on system hardware produced by test program stimulus. The time, required resources, complexity and cost of preparing such test programs is prohibitive.
It would therefore be desirable to provide an efficient arrangement and method that allows data transfer request queues to be controlled, or “throttled”, by way of simple user-defined parameters. Implemented priority schemes can be maintained, but can be selectively bypassed to perform stress tests, or to accommodate peculiar situations which might arise during normal operation. The present invention provides such a solution, and provides these and other advantages and benefits over the prior art.
SUMMARY OF THE INVENTION
The present invention relates to a system and method for selectively controlling the interface throughput of data transfer requests from request sources to request destinations, thereby providing the ability to manipulate data throughput under normal operating conditions, and to provide a means for performing transaction processing testing.
In accordance with one embodiment of the invention, a method is provided for controlling the flow of data transfer requests from various request sources to various request destinations. Each data transfer request is a request for an addressed one of the request destinations to supply a data segment to the requesting source. The data transfer requests from each of the request sources are temporarily stored for future delivery to its addressed request destination. Delivery of the stored data transfer requests to the addressed request destination is enabled according to a predetermined delivery priority scheme. Certain ones of the stored data transfer requests are identified to be selectively suspended from being prioritized and delivered to the addressed request destination. These identified data transfer requests are suspended from delivery for a definable period of time. During this time, the destination addressed by the suspended data transfer requests will not receive any of these requests. Upon expiration of the definable period of time, the suspended data transfer requests, as well as all other stored data transfer requests, are enabled for prioritization and delivery in accordance with the predetermined delivery priority scheme. In this manner, the suspended data transfer requests will gain priority during the period of suspension, and will thereafter be provided to the destination according to their respective priorities.
In accordance with another embodiment of the invention, a method is provided for controlling the flow of data transfer requests during normal system operations of a multiprocessing computing system that has multiple request sources that provide data transfer requests to multiple request destinations. The data transfer requests are prioritized according to a predetermined request dispatch priority scheme. Each data transfer request is a request for an addressed one of the request destinations to supply a data segment to a respective one of the request sources. The method includes periodically performing first data transfer operations between a first request source and a targeted request destination. A second data transfer operation is initiated between a second request source and the targeted request destination, wherein the second data transfer operation is subject to a response timeout limitation. The first data transfer operations are suspended for a user-defined period upon recognition of initiation of the second data transfer operation, and the se
Altera Law Group
Etienne Ario
Johnson Charles A.
Starr Mark T.
Unisys Corporation
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