Coded data generation or conversion – Digital code to digital code converters – With error detection or correction
Reexamination Certificate
1999-03-30
2001-05-08
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
With error detection or correction
C340S398100
Reexamination Certificate
active
06229462
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of digital communications. In particular the present invention discloses a circuit that minimizes the disparity of set and clear bits transmitted across a serial bit channel.
BACKGROUND OF THE INVENTION
A serial bit channel is an information channel that carries digital information as a sequential series of ones (“1”) and zeros (“0”). Since the bits are transmitted sequentially, only one conductor is required to implement a serial bit channel. (However, most implementations use another conductor for ground/reference and may use additional conductors for flow control, timing, etc.)
One simple method of implementing a serial line is to designate a ground voltage value as a clear (“0”) bit and a +5 voltage value as a set (“1”) bit value. In such a system, a long series of set (“1”) bits will cause the physical media of the serial channel to have a positive direct current (DC) bias. Similarly, a long series of clear (“0”) bits will cause the serial channel to become biased towards ground. This biasing in either direction may eventually cause data interpretation errors.
To prevent such data interpretation errors, it would be desirable to limit the disparity between the number of set (“1”) bits transmitted and the number of clear (“0”) bits transmitted.
SUMMARY OF THE INVENTION
A method of minimizing a disparity of set and clear bits transmitted across a serial is disclosed. The method operates by determining a line disparity by examining a first n bit dataword to be transmitted on said serial line, the line disparity specifying a disparity between set bits and clear bits. The method further examines a second n bit dataword to be transmitted to determine a dataword disparity of the second n bit dataword, the data word disparity specifying a disparity between set bits and clear bits in said dataword. The method further generates a third n bit dataword by assigning a complement of the second n bit dataword if the line disparity and said word disparity have a same sign, else assigning the second n bit data word to the third n bit dataword. The method then transmits the third n bit dataword.
REFERENCES:
patent: 4499454 (1985-02-01), Shimada
patent: 4520346 (1985-05-01), Shimada
patent: 4760378 (1988-07-01), Iketani et al.
Bloechel Bradley A.
Dike Charles E.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen John B
Young Brian
LandOfFree
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