Semiconductor device with bonding anchors in build-up layers

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

Reexamination Certificate

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Details

C174S262000, C174S264000, C361S773000, C257S698000

Reexamination Certificate

active

06252178

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to semiconductor devices that enable high temperature wire bonding regardless of the material used for build-up layers.
2. Description of the Related Art
The microelectronics industry has continued to make significant advances in semiconductor device technology. Semiconductor devices are getting smaller, more dense, and run at higher speeds. The semiconductor device typically comprises a chip attached to one or more layers of a printed circuit board (PCB) that is, in turn, plugged into a panel board.
New “Build-Up” technologies are now emerging to provide for the increased density of semiconductor devices. One such technology is the well known surface laminar circuit (SLC) technology. SLC uses photo patterning to embed fine lines of wiring on both sides of a PCB. Multiple build-up levels of fine line wiring can be created on each side of the PCB. SLC technology provides for improved route and escape capabilities due to smaller geometries and via sizes.
Referring to
FIG. 1
, a PCB core
10
is depicted with multiple build-up layers
20
,
25
,
30
,
35
on each side. The SLC process starts with a conventional PCB core such as a FR4 printed wiring board. A photosensitive dielectric (laminate material) is applied over the PCB surface, and small microvias
40
, typically 100 microns in diameter, are formed through the dielectric material to the layer directly below by exposure and developing of the dielectric material. Multiple build-up layers can be formed on each side of the PCB core.
There are a number of different ways to electrically connect chips to the PCB. One advantageous method is to wire bond from the terminals on the chip to bonding pads on the dielectric layer by using thin wires, typically aluminum, gold or copper. Two common methods of bonding the wire to the bonding pads are thermal compression and ultrasonic welding. Thermal compression or high temperature (i.e., 150-190 degrees C.) wire bonding works in many cases, but cannot be performed on photosensitive dielectric materials such as the ones used in the SLC process. The photosensitive dielectric materials are soft and have a low glass transition temperature (T
g
), typically in the range of 80-110 degrees C. The heat generated during wire bonding quickly spreads from the bonding pad to the surrounding dielectric layer. Since the dielectric material has a low T
g
, the dielectric softens causing the bonding pad and other features in the area to move or otherwise become unstable.
Ultrasonic welding or lower temperature wire bonding can be performed at temperatures as low as room temperature, and thus solves the problem of the low glass transition temperature. However, ultrasonic welding presents other problems. The dielectric material is now exposed to the stress of the high frequency ultrasonic energy that is required for ultrasonic welding. The dielectric materials used for the SLC process do not consistently hold up under the mechanical vibrations produced at this high frequency. The materials will often break down, resulting in a much lower manufacturing yield. Ultrasonic welding also requires more expensive machinery than the high temperature wire bonding.
Although thermal compression wire bonding has recently been performed at a lower stage temperature (i.e., 80-95 degrees C.) and with a higher wire bonder frequency, problems with the new technique are confronted that adversely affect the bonding throughput (e.g., from 8-10 bonds/second down to 1-2 bonds/second). In addition, the higher wire bonder frequency requires different wire bonders that are more expensive.
As a result of the foregoing shortcomings of the prior art, it is not possible to combine the robust and commonly used process of high temperature wire bonding with the high density SLC build-up technology. At best, ultrasonic welding can be performed on the SLC packages resulting in a low through put and a high rate of material breakdown.
Thus, there exists a need for a structure and a high yielding process which combines the desirable properties of wire bonding with any high density microvia PCB technology, but which does not unnecessarily add to the cost of the fabrication process.
SUMMARY OF THE INVENTION
It is an advantage of the present invention to provide for a semiconductor device that enables high temperature wire bonding to be used in conjunction with build-up layers having a low glass transition temperature. The addition of bonding anchors that are located under bonding pads and that contact the PCB core layer, provides this advantage by serving as thermal gateways for the heat generated by the wire bonding.
The above and other advantages of the present invention may be achieved in one form by a semiconductor device having one or more build-up layers formed over a PCB core layer, and one or more anchors passing through the thickness of the build-up layers such that the anchors contact the PCB core layer. A die attach pad is provided on the upper surface of the build-up layers and a semiconductor device chip is attached to this pad. A plurality of bond pads are formed on the upper surface of the build-up layers such that the bond pads are located immediately above the anchors. The chip is electrically connected to the bond pads by the commonly known technique of high temperature or thermal compression wire bonding.


REFERENCES:
patent: 5263243 (1993-11-01), Taneda et al.
patent: 5896276 (1999-04-01), Tamura et al.
patent: 6014318 (2000-01-01), Takeda
patent: 6156980 (2000-12-01), Peugh et al.

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