Gate biasing arrangement to temperature compensate a...

Miscellaneous active electrical nonlinear devices – circuits – and – External effect – Temperature

Reexamination Certificate

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Details

C327S108000, C327S427000

Reexamination Certificate

active

06288596

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistors and more specifically to a gate biasing arrangement for an RF power LDMOS field effect transistor for temperature compensation of its quiescent current.
BACKGROUND OF THE INVENTION
The appended drawing,
FIG. 1A
illustrates a conventional way of biasing the gate G of an RF power LDMOS field effect transistor
1
to a gate voltage VG that gives a desired value of quiescent current IDQ of the transistor
1
. The RF signal is supplied to the gate G via a terminal
2
.
To bias the gate G of the transistor
1
, a fixed resistor R
1
is connected between the gate G and the source S, which normally is connected to ground, and a variable resistor R
2
is connected between the gate G and a terminal at a positive voltage. By means of the resistor R
2
, the gate voltage VG is adjusted to a value that gives the desired quiescent current IDQ through the transistor
1
.
The value of the quiescent current IDQ is commonly chosen to give a flat gain versus output power characteristic. Any deviation from this chosen IDQ value will degrade the linearity performance of the transistor.
For a given value of the gate voltage VG, the quiescent current IDQ is temperature dependent. Consequently, temperature changes will cause degradation of the performance of the transistor
1
.
The temperature coefficient of the transistor's quiescent current is a function of the gate bias voltage. The relatively low values of the gate bias voltage VG that are normally used, gives a positive temperature coefficient, i.e. the quiescent current IDQ increases with temperature.
A common approach to reduce the variation of the quiescent current IDQ with changes in temperature is to introduce a discrete diode DI in series with the resistor R
1
as shown in FIG.
1
B. The voltage drop across the diode decreases as the temperature increases and thus partially eliminates the RF transistor's quiescent current temperature dependence.
There are however two apparent drawbacks of using a diode for temperature compensation. Firstly, the temperature characteristic of a diode does not exactly track the temperature characteristic of an RF LDMOS transistor. Secondly, it is hard to achieve a good thermal coupling between a discrete diode and the transistor, resulting in different temperatures for the two components.
SUMMARY OF THE INVENTION
The object of the invention is to eliminate the temperature dependency of the quiescent current of the power transistor.
This is attained by controlling the gate bias voltage of the power transistor by means of the output voltage of a biasing transistor residing on the same silicon chip as the power transistor, and by interconnecting the gate and drain of the biasing transistor and feeding it with a constant current from external circuitry.
Since the gate and drain of the biasing transistor are connected to each other, the gate voltage of the biasing transistor will automatically adjust to sustain the forced drain current. Due to the inherent temperature dependence of the biasing transistor, the gate bias voltage will decrease as temperature increases. Consequently, the gate bias voltage of the power transistor will decrease with increasing temperature resulting in a constant quiescent current IDQ.
The invention will also handle the case where the gate bias is higher, resulting in a negative temperature coefficient of the quiescent current.


REFERENCES:
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 5027082 (1991-06-01), Wisherd et al.
patent: 5045822 (1991-09-01), Mohwinkel
patent: 5204561 (1993-04-01), Rischmüller
patent: 5633610 (1997-05-01), Mackawa et al.
patent: 5764098 (1998-06-01), Taga et al.
patent: 5808496 (1998-09-01), Thiel
patent: 6150852 (2000-11-01), Aparin
patent: 0606094A2 (1994-07-01), None

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