Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-04-16
2001-04-10
Bueker, Richard (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345420
Reexamination Certificate
active
06214740
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a dry-etching apparatus for semiconductor devices.
BACKGROUND OF THE INVENTION
In recent years, the integration degree of semiconductor devices has risen remarkably. The increase of the integration degree is sustained by advances in process techniques. Especially, advances in photolithography techniques and dry etching techniques play a great role for the rise of the integration degree. In recent dry-etching techniques, a tendency can be observed toward the active use, from the view point of miniaturization, of a low gas pressure, high density plasma. Considering such a background, dry-etching apparatus using an electron cyclotron resonance plasma, an inductive coupling type plasma or a helicon wave excitation plasma have been developed and sold (see for example: “Semiconductor World” Oct. issue 1993, pp. 68-75).
Below, an example for a conventional oxide film etching apparatus is explained with reference to
FIG. 1
, which shows an apparatus using an inductive coupling type plasma.
In
FIG. 1
, numeral
1
is an induction coil and numeral
2
is a high frequency power source, which supplies the induction coil
1
with high frequency electricity. Numeral
3
is a lower electrode and numeral
4
is a high frequency power source, which supplies the lower electrode
3
with high frequency voltage. Numeral
5
is an upper silicon electrode and numeral
6
is a silicon substrate placed on the lower electrode
3
and arranged in parallel to the upper silicon electrode
5
within at reaction chamber
7
. Numeral
8
is a pressure control valve and numeral
9
is an exhaust pump, by which a predetermined pressure is maintained in the reaction chamber
7
. Numeral
10
is a gas bottle, supplying C
2
F
6
to the reaction chamber
7
through a mass flow
13
. Numeral
11
is a heater, which maintains the upper silicon electrode
5
at a constant temperature. Numeral
12
is a silicon ring, which is arranged to enclose the silicon substrate
6
on the lower electrode
3
. Numeral
13
is a mass flow and numeral
14
is a matcher to attain impedance matching between the high frequency power source
4
and the lower electrode
3
.
C
2
F
6
is introduced into the reaction chamber
7
from the gas bottle
10
and maintained at a predetermined pressure. A plasma is generated in the reaction chamber
7
by supplying the induction coil
1
with high frequency electric power from the high frequency power source
2
. Ions from the plasma are attracted by impressing a bias voltage onto the lower electrode
3
with the high frequency power source
4
, so that the silicon substrate
6
is etched.
The silicon ring
12
and the upper silicon electrode
5
(which are referred to as silicon members below) realize a high etching speed ratio of the oxide film against the silicon substrate
6
by decreasing the fluorine in the plasma due to a reaction with silicon (see
FIG. 2
B). This silicon member has a smooth surface, and as is shown in
FIG. 3B
, the average roughness of the irregularities H of the surface is about 0.1 &mgr;m.
Numeral
15
of
FIG. 4
is an example for the relationship between operating time T and selectivity ratio R for the etch rate of the oxide film of the silicon substrate with respect to the resist, when conventional silicon members with a smooth surface are used.
A constant time period is necessary so that the silicon members can scavenge halogen elements. After such aging is finished, a stable etch rate is attained.
However, as can be gathered from numeral
15
of
FIG. 4
, in a conventional manufacturing apparatus using silicon members with a smooth surface, a long period of time is necessary to stabilize the selectivity ratio R for the etch rate of the oxide film with respect to the resist. That means, there was the problem that a long aging time is necessary to put the silicon members into a condition where they can scavenge halogen elements.
SUMMARY OF THE INVENTION
In order to solve the problems of the prior art, it is a purpose of the present invention to provide a manufacturing apparatus for semiconductor devices, which can abbreviate the aging time by having a halogen scavenger with irregularities on its surface.
In order to attain this purpose, a manufacturing apparatus for semiconductor devices according to the present invention comprises a halogen scavenger having tiny irregularities on its surface in a reaction chamber of a dry-etching apparatus and the average roughness of those tiny irregularities is 1-1000 &mgr;m.
Because such a manufacturing apparatus for semiconductor devices comprises a halogen scavenger having irregularities on its surface, the effective surface area for halogen elements is maintained from an initial condition, so that the aging time is abbreviated.
When the average roughness of those tiny irregularities in the manufacturing apparatus for semiconductor devices is 1-1000 &mgr;m, the aging time can be abbreviated and an unfavorable influence such as an etching stop can be prevented.
It is preferable that the average roughness of the tiny irregularities in the manufacturing apparatus for semiconductor devices is 1-10 &mgr;m.
It is preferable that the halogen scavenger in the manufacturing apparatus for semiconductor devices comprises at least one material selected from the group consisting of silicon and carbon.
It is preferable that the halogen scavenger in the manufacturing apparatus for semiconductor devices is a silicon ring arranged around the silicon substrate to be etched.
It is preferable that the halogen scavenger in the manufacturing apparatus for semiconductor devices is an upper silicon electrode arranged above the silicon substrate to be etched.
It is preferable that the irregularities in the manufacturing apparatus for semiconductor devices are produced by wet-etching.
It is preferable that a gas used for dry-etching in the manufacturing apparatus for semiconductor devices is C
2
F
6
.
REFERENCES:
patent: 5362361 (1994-11-01), Tatsumi
patent: 5474649 (1995-12-01), Kava
patent: 5556500 (1996-09-01), Hasegawa
patent: 5556501 (1996-09-01), Collins
patent: 6007673 (1999-12-01), Kugo et al.
patent: 0 601 468 (1994-06-01), None
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patent: 61-276322 (1986-12-01), None
patent: 62-47130 (1987-02-01), None
patent: 3-138381 (1991-06-01), None
Wolf, Stanley and Richard Tauber. Silicon Processing. vol. 1, Ch. 16 p. 581-582, 1986.
Imai Shin-ichi
Jiwari Nobuhiro
Nikoh Hideo
Bueker Richard
Fieler Erin
Matsushita Electronics Corporation
Merchant & Gould P.C
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