Phase splitter

Details Phase splitter Phase splitter

1999-04-21

2001-09-18

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S259000

Reexamination Certificate

active

06292042

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a phase splitter for receiving a clock signal and for providing clock signals of similar and opposite phases when compared to the received clock signal at the same time.
2. Discussion of the Related Art
The clock signal, when used as a driving signal for a system, should have a high frequency for driving the system faster. However, since clock signal frequencies are limited, two clock signals are sometimes jointly used as a received clock signal clk_in to increase system speed, i.e., a clock signal clk having a phase equal to the received clock signal clk_in and a clock signal clk_b having a phase that is inverted with respect to the received clock signal clk_in. A background art phase splitter conventionally used to achieve these joint clock signals will be explained with reference to the attached drawings.
FIG. 1
illustrates the background art phase splitter.
Referring to
FIG. 1
, the background art phase splitter is provided with a first inverter
11
for inverting a phase of a received signal, a second inverter
12
for inverting an output of the first inverter
11
to provide a clock signal having a phase equal to the received signal at the end, a third inverter
13
for inverting a phase of the received signal, a fourth inverter
14
for inverting an output of the third inverter
13
, and a fifth inverter
15
for inverting an output of the fourth inverter
14
to provide a clock signal having a phase opposite to the received signal. Each of the inverters has a PMOS transistor and an NMOS transistor.
The operation of the aforementioned background art phase splitter will be explained with reference to the timing diagram of FIG.
2
. There is a delay, as much as td
1
, from reception of a clock signal clk_in to an output of a clock signal clk having the same phase. That is, the received clock signal clk_in is phase inverted by the first inverter
11
and phase inverted again by the second inverter
12
. Accordingly, though a signal from the second inverter
12
has a phase equal to the received clock signal, there is a delay of as much as td
1
caused by the first and second inverters
11
and
12
. On the other hand, there is a delay of as much as td
2
between reception of the clock signal clk_in to an output of an inverted clock signal clk_b. That is, the received clock signal clk_in is phase inverted by the third inverter
13
, inverted a second time by the fourth inverter
14
, and inverted a third time by the fifth inverter
15
. At the end, the clock signal clk_b has an inverted phase and a delay of as much as td
2
with respect to the received clock signal clk_in. Thus, the background art phase splitter provides a clock signal having a phase equal to a received clock signal and a clock signal having a phase opposite to the received clock signal using inverters.
However, the background art phase splitter has at least the following problems.
The two clock signals, i.e., clk and clk_b have a timing mismatch of as much as td
2
. Even if sizes of transistors in the inverters are adjusted to take the timing mismatch into consideration, the timing mismatch is still likely to exist due to variations of a fabrication process or variations of a voltage and temperature.
Moreover, conventional phase splitters divided an input clock signal clk_in into two signals, a first clock signal clk having a phase equal to the input clock signals clk_in, and a second clock signal clk_b having a phase that is opposite to the input clock signal clk_in as shown in
FIG. 1
, and even numbered series arrangement of inverters was used to generate first clock signal clk, while an odd numbered series arrangement of inverters was used to generate second clock signal clk_b. Because each inverter introduces some delay (e.g., shown in
FIG. 2
as td
2
or ½ of td
1
), the even numbered and odd numbered series arrangements generate clock signals having different delays relative to the input clock signal clk_in. In other words, the first clock signal CLK is delayed by two units of inverter delay, while the second clock signal, clk_b is delayed by three units of inverter delay. For this reason, as shown in
FIG. 2
, although first and second clock signals clk and clk_b each have a phase equal to the phase of the input signals clk_in, first and second clock signals clk and clk_b are not synchronous with each other. This timing mismatch is not easily corrected during the phase splitter fabrication.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a phase splitter that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The present invention provides a phase splitter which can prevent a timing loss from a presentation timing mismatch of a clock signal having a phase equal to, and a clock signal having a phase inverted from a received signal, which phase splitter is not sensitive to variations of a fabrication process, voltages, temperatures, and the like.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. Other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the phase splitter includes a semiconductor device for providing a signal of the same phase and a signal of an inverted phase with respect to a received signal, the semiconductor device including a first, and a second transmission gates for providing the received signal, and a signal of an inverted phase with respect to the received signal at being determined of a turning on/off by a signal from an inverter which inverts the received signal, and a third, and a fourth transmission gates for providing the received signal, and a signal of the same phase with respect to the received signal at the same time with the providing of the signal of an inverted phase at being determined of a turning on/off by the signal from the inverter.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4456837 (1984-06-01), Schade, Jr.
patent: 5047659 (1991-09-01), Ullrich
patent: 5592115 (1997-01-01), Kassapian
patent: 5637998 (1997-06-01), Kushihara
patent: 5852378 (1998-12-01), Keeth
patent: 5867043 (1999-02-01), Kim

Affiliated with

Also associated with

Rating

Phase splitter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase splitter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase splitter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2479096