Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1998-07-02
2001-04-24
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S270000
Reexamination Certificate
active
06222406
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a semiconductor memory system, and, particularly, the invention relates to a technique effective for use in devices which need minute or micro and highly-accurately controlled delay signals. This invention also relates to a clock synchronous circuit having a quick response and to high accuracy and a technique effective for use in a semiconductor integrated circuit device, such as a synchronous DRAM (Dynamic Random Access Memory) equipped with a clock synchronous circuit.
An array oscillator disclosed by ISSCC has been known as an example of a circuit for obtaining a time resolution of a few 10 psec (picoseconds). In this known type of array oscillator, the same ring oscillators are arranged in large numbers in a column direction and are connected in a ring form using one input of each individual stage as two inputs, and the outputs of the respective stages are respectively supplied to other inputs of adjoining stages, and they are also connected in ring form even in a row direction.
Such an oscillator has been described in ISSCC 93/ANALOG TECHNIQUES/PAPER TA7.5, pp. 118-119, 1993 and ISSCC/SESSION 18/MEMORIES WITH SPECIAL ARCHITECTURES/PAPER FP18.5, pp 308-309, 1995, and Japanese Published Unexamined Patent Application No. Hei 8-78951.
A clock synchronous circuit excluding a feedback loop like a synchronous mirror delay (SMD) is characterized in that the time (lock time) necessary for synchronization is short, as in the case of 2 to 3 cycles. According to this feature, the lock time can be shortened by measuring the cycle of an input clock as the number of stages of delay circuits or coarse delays. The time resolution of this measuring circuit is determined depending on a delay time per stage corresponding to a component of each delay circuit. The time resolution is normally on the order of a delay time corresponding to two stages of CMOS inverters. Japanese Published Unexamined Patent Application No. Hei 8-237091 is an example of a clock synchronous circuit using such an SMD.
SUMMARY OF THE INVENTION
In order to speed up a semiconductor memory such as a dynamic RAM (Random Access Memory) or the like, memory access times as seen from a memory controller for generally controlling plural RAMs are made uniform by making uniform the signal transfer delays on a substrate mounted between such RAMs and the memory controller, in other words, in anticipation of the signal propagation delays on the mounted substrate, increasing delay times thereinside when such signal delays are small and decreasing delays thereinside when such signal delays are large, whereby it is possible to easily ensure the time (window) required to allow data capturing occupied in a cycle time and speed up the memory cycle time. If semiconductor memories are implemented on a mounting substrate having signal wires or interconnections whose characteristic impedance is 50 &OHgr;, at 1 centimeter (cm) intervals, the signal propagation delay time encountered between each individual semiconductor memories becomes about 50 psec. It is therefore necessary to provide delay circuits each having a high-precision time resolution of a few 10 psec inside the respective semiconductor memories with a view toward making uniform the signal transfer delays between the memory controller and the respective semiconductor memories as described above.
The inventors of the present invention have discussed the utilization of the above-described array oscillator to implement the delay circuits each having the above-mentioned high-precision time resolution. In the array oscillator, however, delay signals having delays equal to each other by the number of respective stages are to be formed for the number of logic stages lying in a row direction. However, in a circuit formed on an actually-available semiconductor substrate, each signal delay encountered in the row direction will not be recognized to have satisfactory linearity, and the signal delay will become fast in one logic stage or slow in another logic stage. Thus, it has been found that even if the principle of the above-described array oscillator is used as it is, the above-mentioned micro and uniform signal delay in the order of a few 10 psec cannot be obtained.
It has been recognized by the inventors that a problem arises in that, if it is assumed that minute and uniform signal delays are obtained and logic circuits are disposed on a semiconductor substrate in a lattice form along row and column directions, then signal paths for taking out output signals cannot be provided evenly in the cases: where delay signals are respectively outputted from logic circuits disposed inside the lattice form and where delay signals are respectively outputted from logic circuits disposed outside the lattice form.
Since the array oscillator is made up of ring oscillators, the start-up time between its deactivated state and stabilization of its operation is relatively long. It has been evident from the discussions by the present inventors that a problem arises in that the formation of a desired signal at high speed encounters some difficulties.
A first object of this invention is to provide a semiconductor integrated circuit device provided with a circuit for forming signals each having a minute and high-accuracy time resolution. A second object of this invention is to provide a semiconductor integrated circuit device having a delay circuit disposed on a semiconductor substrate with efficiency and which is capable of forming delay signals each having a micro and high-accuracy time resolution. A third object of this invention is to provide a semiconductor memory system which is capable of implementing the input and output of data at high speed.
A fourth object of this invention is to provide a semiconductor integrated circuit device provided with a circuit for forming signals each having a small and high-accuracy time resolution at high speed.
A summary of a typical one of the features disclosed according to the first through fourth objects of the invention will be described in brief as follows:
There is provided a semiconductor integrated circuit device comprising:
at least one delay circuit including,
M signal lines for receiving a first input signal to successively-delayed M (M=2, 3, 4, . . . )th input signals therein; and
M logic gate circuit groups extending from a first logic gate circuit group corresponding to the first input signal to an Mth logic gate circuit group corresponding to the Mth input signal, and
wherein each of the individual logic gate circuit groups have N logic gate circuits extending from a first logic gate circuit to an N (N=3, 4, 5, . . . )th logic gate circuit, each logic gate circuit having a first input terminal, a second input terminal and an output terminal,
coupling elements are provided between the first and second input terminals of the logic gate circuits respectively,
the first to Nth logic gate circuits in each logic gate circuit group are tandem-connected to the output terminals through the first input terminals, respectively,
the M signal lines are connected to the first input terminals of the first logic gate circuits in their corresponding logic gate circuit groups,
first input terminals of L (L=1, 2, 3, . . . )th logic gate circuits in each of the first logic gate circuit group to M−1th logic gate circuit group are connected to second input terminals of Lth logic gate circuits in the next logic gate circuit group,
first input terminals of predetermined logic gate circuits in the Mth logic gate circuit group are connected to second input terminals of predetermined logic gate circuits in the first logic gate circuit group, and
successively-delayed output signals are respectively obtained from the output terminals of a plurality of the Nth logic gate circuits.
A summary of another typical one of the features disclosed in association with the first to fourth objects of the inventions will be described in brief as follows:
There is pr
Aoki Hideyuki
Aoki Masakazu
Noda Hiromasa
Tanaka Hitoshi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lam Tuan T.
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