Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-04-03
2001-07-10
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185120, C365S185110, C365S185090
Reexamination Certificate
active
06259630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device, such as a flash memory, including a number of memory cells for storing data bits that are written or erased at a time.
2. Description of the Related Art
Nonvolatile semiconductor memory devices, such as a flash memory, are often used as storage of input data, like files. When writing at a time data bits to a number of memory cells of the nonvolatile semiconductor memory device, page buffers are used to temporarily store the data bits at the same time. The page size of the page buffers is, for example, 512 bytes. Also, when erasing at a time data bits from a number of memory cells of the nonvolatile semiconductor memory device, the page buffers are used to temporarily store the data bits at the same time. The page size of the page buffers is, for example, 8 K bytes.
Generally, after the data bits are written to or erased from the memory cells of the nonvolatile semiconductor memory device, a defect in any of the memory cells may arise with a certain probability. In order to check if a defect in the memory cells of the memory device has occurred, a verification operation is automatically performed on the memory device every time the memory device is written to or erased.
For example, a write verify operation is repeated several times on the memory device when the data bits are written to the memory cells, which produces a verify status information that indicates whether the data bits are properly written to the memory cells. An erase verify operation is repeated several times on the memory device when the data bits are erased from the memory cells, which produces a verify status information that indicates whether the data bits are properly erased from the memory cells.
If a certain command is externally input to the memory device, external devices can have access to the verify status information stored in the memory device.
FIG. 16
shows a conventional flash memory which can provide the verify status information to external devices.
As shown in
FIG. 16
, the conventional flash memory includes a controller
300
, a memory array
301
, a plurality of page buffers
302
, a verification circuit
303
, an output circuit
306
, and a latch circuit
307
.
The controller
300
controls the entire conventional flash memory.
The memory array
301
includes an array of memory cells in columns and rows, and includes word lines and bit lines provided in orthogonal directions, the memory cells for each column sharing one of the bit lines, and the memory cells for each row sharing one of the word lines.
The plurality of page buffers
302
are connected to the memory cells of the memory array
301
via the bit lines. The plurality of page buffers
302
are divided into “M” subblocks
302
-
0
through
302
-(M−1) where M is a given positive integer. Each of the M subblocks contains a number of page buffers
302
. The M subblocks of page buffers
302
-
0
through
302
-(M−1) are provided to temporarily store the data bits which are written to or erased from the memory cells of the memory array
301
.
The output circuit
306
is divided into “N” subblocks
306
-
0
through
306
-(N−1) where N is a given positive integer. The N subblocks of the output circuit
306
are provided to output N pieces of data (or datal through data(N−1)) which are received from a data bus.
The conventional flash memory of
FIG. 16
includes “N” input/output pins
100
through IO(N−1), and the number M of the page buffer subblocks may be the same as the number N of the input/output pins. The subblocks
306
-
0
through
306
-(N−1) of the output circuit
306
respectively correspond to the input/output pins
100
through IO(N−1).
The verification circuit
303
is provided to output a verify status information indicating the result of a write verify operation or an erase verify operation performed on the memory cells in the memory array
301
. The operation of the verification circuit
303
is controlled by the controller
300
.
The verification circuit
303
is connected to the M subblocks of the page buffers
302
-
0
through
302
-(M−1) via a common PV signal line. After the write verify operation is performed, the verification circuit
303
receives a write verify signal PV sent on the common PV signal line by the page buffers
302
-
0
through
302
-(M−1). When at least one of the memory cells corresponding to the above page buffers is found defective, the write verify signal PV is set to the low level. When all of the memory cells corresponding to the above page buffers are found normal, the write verify signal PV is set to the high level. The verification circuit
303
outputs a verify status signal VPASS in response to the write verify signal PV, the verify status signal VPASS at this time indicating the result of the write verify operation.
Further, the verification circuit
303
is connected to the M subblocks of the page buffers
302
-
0
through
302
-(M−1) via a common EV signal line. After the erase verify operation is performed, the verification circuit
303
receives an erase verify signal EV sent on the common EV signal line by the page buffers
302
-
0
through
302
-(M−1). When at least one of the memory cells corresponding to the above page buffers is found defective, the erase verify signal EV is set to the low level. When all of the memory cells corresponding to the above page buffers are found normal, the erase verify signal EV is set to the high level. The verification circuit
303
outputs a verify status signal VPASS in response to the erase verify signal EV, the verify status signal VPASS at this time indicating the result of the erase verify operation.
The verify status signal VPASS output by the verification circuit
303
is delivered to the subblock
306
-
0
(corresponding to the pin IO
0
) of the output circuit
306
via the latch circuit
307
. When a defective cell in the memory cells is found as the result of the verify operation, a signal, indicating the content of the verify status signal VPASS, is output from the pin IO
0
of the conventional flash memory to an external device.
However, there exist some circumstances in which the memory device can still be used as the storage of input data, even when the output signal of the pin IO
0
indicates the occurrence of a defect in the memory array. For example, if the external device is equipped with an error correction circuit, or if the defective cell is located in an unrelated region of the memory array, the memory device can still be used for storage of input data. In such circumstances, it is necessary to quickly identify the location of a defective cell in the memory device.
In the above-mentioned conventional flash memory, the location of the defective cell in the memory array is not yet identified at the time when the output signal of the pin IO
0
indicates the occurrence of a defect in the memory array. In order to identify the location of the defective cell, a predetermined command is input to the conventional flash memory, and the contents of the page buffers
302
-
0
through
302
-(M−1) must be read out from the conventional flash memory. This read-out operation is performed on the above page buffers in accordance with an externally supplied clock.
If the defective cell are located at the last address of the memory array as the result of the write verify operation (the page size is 512 bytes), a time period corresponding to 512 clocks is needed to perform the read-out operation that identifies the location of the defective cell in the memory array. If a cycle time of the clock are 50×10
−9
seconds, the time period corresponding to the 512 clocks needed for the above case amounts to 25.6×10
−6
. In a case of the erase verify operation, the needed time period will be further increased.
Accordingly, it is difficult for the conven
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Tran Andrew Q.
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