Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-10-20
2001-05-15
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06233594
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention generally relates to analog-to-digital converters, and more particularly to an improved decimation filter for use with an oversampling analog-to-digital converter.
2. Discussion of the Related Art
As is known, oversampling analog-to-digital converters (ADCs) generally consist of two parts: an analog modulator and a digital filter. The analog modulator receives an analog signal and produces a serial data stream having a bit rate which is much greater than the Nyquist sampling frequency. The quantization noise of the analog modulator is shaped to minimize the noise in the passband of interest, at the expense of higher noise outside of this passband. This is as opposed to distributing the noise evenly between DC and the modulator sampling frequency. The digital filter portion of the ADC is operable to filter and decimate the modulator representation of the analog input. Since the modulator quantization noise is shaped, the digital filter must filter this out-of-band quantization noise and reduce the output word frequency to twice the effective Nyquist frequency. Decimation is a well-known technique that is utilized in most oversampling ADCs.
In some applications utilizing decimation, the output sampling rate must be set at one of a plurality of sampling rates. In order to provide for these different sampling rates, an ADC needs to have the ability to select one of a plurality of decimation rates to provide the selected output sampling rate. This must either be done by providing a plurality of ADCs with fixed and separate decimation rates or to perform some control of the digital filter to effect a variable decimation rate architecture.
Conventional digital filters in ADCs utilize some form of digital signal processor utilizing multiple stages of digital filtering. These stages of digital filtering typically utilize a finite impulse response (FIR) or infinite impulse response (IIR) filter topology which requires at minimum a multiplier and an accumulator and stored filter coefficients that define the transfer function of the filter. The data is processed with the multiplier and accumulator utilizing the stored filter coefficients. Each set of filter coefficients is designed to provide a specific decimation rate and filter transfer function. In order to provide a variable decimation rate, it is necessary to process data through multiple filter stages with the number of filter stages varied. With conventional digital filter processors having unlimited processing power, select filter topologies and the order thereof can be realized. However, an ADC that is incorporated into an integrated circuit has limited silicon real estate and limited power budget available and, therefore, incorporating the full power of a digital signal processor is not feasible. Typically, oversampling ADCs have utilized a fixed decimation architecture (usually sinc or comb filter architecture) to realize a desired filter transfer function.
A decimation filter is arranged to reduce the sampling frequency of a digital information signal such that no aliasing occurs. Various structures and embodiments of decimation filters are known. The common practice is to use a sinc or comb filter due to its simplicity and efficiency. The transfer function of sinc filter is defined by equation 1.
H
(
z
)
=
{
1
-
z
-
N
1
-
z
-
1
}
k
=
{
∑
i
=
0
N
-
1
z
-
1
}
k
,
(
Equation
1
)
where N is the decimation ratio and k is the order of the sinc filter. A scaling factor may also be included in the algorithm to facilitate the hardware implementation.
The order of the sinc filter should be one order higher than the delta-sigma modulator in order to filter out the spectrally shaped quantization noise. The decimation ratio is usually chosen to be one-fourth of the total decimation ratio (or oversampling ratio OSR) due to the consideration of the attenuation at the upper end of the passband. Further decimation by a factor of four can be done by an ordinary filter since the data rate is already greatly reduced. This arrangement represents an adequate trade-off, considering the complexity and the compensation for the droop due to the sinc filter. Usually, the sinc filter consumes a relatively large amount of power, due to the high data rate and the FIR filter is relatively less power consuming due to the reduced data rate, in spite of the increased complexity. In some applications, the attenuation at the upper end of the passband is acceptable, we can exclusively use sinc filer for decimation. For example,
FIG. 1
is a block diagram that depicts a well-known structure of a decimation filter. Due to the high input data rate, the decimation filter uses a sinc function as a first stage, followed by a FIR filter.
As is also known, various manners and structures are known to realize this sinc filter. One way of implementing the function of Equation 1 is through the use of a look-up table. More specifically, a memory device, such as a ROM, may be used to store the coefficients to perform a direct convolution. This manner of implementation, however, is costly to implement, in that it demands a relatively large amount of chip area, especially when N and k are large. Another related manner of implementing the function of Equation 1 is to perform direct convolution by using an up/down counter to generate the coefficients, rather than storing them in a ROM to save chip area. However, under this approach, power consumption is relatively large due to the high data rate of operation.
A more popular architecture for realizing the sinc (decimation) filter utilizes a recursive, infinite impulse response (IIR) filter in connection with an FIR filter. A structure realizing this is shown in FIG.
2
. The IIR portion operates at the oversampling frequency. After the IIR portion, the data rate is reduced by a factor of N, and therefore the FIR portion operates at the decimated frequency. Rearranging Equation I yields the Equation 2 below:
H
(
z
)
=
{
1
-
z
-
N
1
-
z
-
1
}
k
=
{
1
1
-
z
-
1
}
k
·
{
1
-
z
-
N
}
k
.
(
Equation
2
)
As will be appreciated from Equation 2, the IIR portion of the equation has multiple poles on the unit circle, and is therefore unstable. A residue algorithm must be applied in order to achieve proper operation, which implies only the residue needs to be stored and the accumulation may overflow. To preserve the accuracy, the data length stored in the registers of the IIR portion must be no less than m+k·log
2
N, where m is the input data length. It will be appreciated that many operations must be performed at the highest data rate, resulting in a relatively large power consumption. In addition, the recursive loop limits the overall speed of operation.
Another embodiment for implementing the sinc filter function filter is through the use of a non-recursive architecture, as illustrated in FIG.
3
. Assuming that N=2
M
, then the transfer function becomes:
H
(
z
)
=
{
1
-
z
-
N
1
-
z
-
1
}
k
=
∏
i
=
0
M
-
1
{
1
+
z
-
2
i
}
k
.
(
Equation
3
)
A significant advantage of the non-recursive architecture is that data rate decreases stage by stage. Although the data rate is high, the data length is relatively short. At high data rates, only the simple FIR filtering with short data length is performed. This results in considerable increase in speed and decreases the power dissipation. However, the non-recursive architecture of
FIG. 3
requires a decimation ratio that is a power of two, since each stage decimates by a factor of two. This also limits the programmable flexibility of the filter design. Another drawback of this technique is the chip area when a large decimation ratio is required. It is seen in
FIG. 3
that when we increase the decimation ration by a factor of 2, we need one more stage to realize it. Since at the later stages, the data length is increased, the chip area increases significantly though the increase in power consump
Keller Peter D.
Tan Nianxiong
Globespan, Inc.
Mai Tan V.
Thomas Kayden Horstemeyer & Risley
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