System and method for minimizing clock cycles lost to...

Image analysis – Image compression or coding

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C348S420100

Reexamination Certificate

active

06205250

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to digital video processors. More particularly, the present invention relates to a system for encoding and decoding image representative picture elements (“pixels” or “pels”) in a block-based image processor.
BACKGROUND OF THE INVENTION
Memory management and memory reduction are important aspects in the design and operation of image processors. For example, television systems may use image processors using the MPEG-2 Standard. The MPEG (Motion Picture Experts Group) signal compression standard (ISO/IEC 13181-2, May 10, 1994) is a widely accepted image processing standard which is well-suited for satellite, cable and terrestrial broadcast systems employing high definition television (HDTV) processing among other forms of image processing. HDTV receivers require 96 megabits or more of memory to temporarily store decoded MPEG video frames prior to display, as part of the process of motion estimation and compensation for accurate image reconstruction.
Systems which reconstruct images from decoded MPEG information typically employ Differential Pulse Coded Modulation (DPCM). In DPCM, processing as typically used in an MPEG decoder, a processor generates a prediction from the actual pixel value resulting in a difference. This difference, known as the prediction error, is generally smaller than the original pixel or prediction values, so quantizing and storing the difference rather than the original pixel value saves memory. Ang, et al., “Video Compression Makes Big Gains,” IEEE Spectrum, October, 1991, describes an MPEG encoder and decoder.
During decoding, a dequantizer regenerates substantially the same prediction from previously decoded pixels. Only a difference value and the prediction are needed to decode and reconstruct the current pixel. The prediction is often partially or wholly based on the previous pixel, which itself was decoded and reconstructed form the preceding pixel. For a more complete description of such predictors and their operation, see Jain, A.,
Fundamentals of Digital Image Processing
, Prentice-Hall, Inc., p. 484 (1989).
Accurately representing the first pixel in a block during image block compression avoids propagating prediction error throughout the entire block of pixels. In smooth areas, (e.g., a display area which has subtle changes in color, objects or the like), noise contamination of the first pixel may produce artifacts which a viewer may find unacceptable. Therefore, the first pixel processed should be represented by a sufficient number of bits when stored in memory to ensure accurate image reconstruction. In this operation, overhead bits are stored at the beginning of each compressed block of pixel data. Processing these overhead bits usually requires extra clock cycles, or alternatively, additional circuitry.
SUMMARY OF THE INVENTION
The present invention provides a video processing system using a method of stripping a predetermined number of overhead bits from a data block while producing a pixel for each clock cycle, but at the same time not increasing the size of a shift register or decreasing bandwidth. A system according to the present invention satisfies these objectives. The present invention is described in detail below, with reference to the drawings.


REFERENCES:
patent: 4451916 (1984-05-01), Casper et al.
patent: 5416615 (1995-05-01), Shirota
Ang., et al., “Video Compression makes big gains”, IEEE Spectrum, Oct. 1991, pp. 16-19.
Jain, “Fundamentals of Digital Image Processing”, Prentice-Hall International, Inc., 1989, pp. 476-498.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System and method for minimizing clock cycles lost to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for minimizing clock cycles lost to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for minimizing clock cycles lost to... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2476047

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.