Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-02-18
2001-04-10
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S389000, C326S017000, C326S028000, C326S082000
Reexamination Certificate
active
06215340
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a driver circuit for a signal line and, more particularly, to a signal transition accelerating driver of the type driving a signal line in response to an input data signal and accelerating the potential level on the signal line.
DESCRIPTION OF THE RELATED ART
In an electric circuit, a signal line usually has a large time constant, and the large time constant renders the signal transition on the signal line gentle. In order to speed up the signal transition, a signal transition accelerating driver is connected to the signal line. A typical example of the signal transition accelerating driver is disclosed in “Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnection Signals of Sub-quarter Micron ULSI”, 1995 Symposium on VLSI Circuits Digest of Technical Papers, and another example is disclosed in Japanese Patent Publication of Unexamined Application No. 8-186482. These examples detect a signal transition, and accelerate it.
A bus system is associated with plural signal transition accelerating drivers as disclosed in Japanese Patent Publication of Unexamined Application No. 9-50693. The signal transition accelerating drivers are selectively activated for driving bus lines, and non-selected signal transition accelerating drivers assists the signal transition on the bus line.
Other related arts already known are described in Japanese Patent Publication of Unexamined Application Nos. 6-59757 and 8-102655. The prior art disclosed in Japanese Patent Publication of Unexamined Application No. 6-59757 relates to a voltage controlled buffer circuit. Japanese Patent Publication of Unexamined Application No. 6-59757 is corresponding to Japanese Patent Application No. 5-172072, and the Japanese Patent Application claimed the convention priority from U.S. Ser. No. 08/902,614. The voltage controlled buffer circuit samples the voltage on a signal line, and compares the sampled voltage with a reference voltage for producing a control signal. With the control signal, the voltage controlled buffer circuit controls the signal rise time and the signal decay time on the associated signal line in order to keep the signal driving speed constant. Another prior art disclosed in Japanese Patent Publication of Unexamined Application No. 8-102655 relates to a bus line driver incorporated in a semiconductor memory device, and a voltage controller is incorporated in the bus line driver. The voltage controller changes the bus line to an intermediate voltage before a signal transition in order to reduce the load of the bus line driver.
FIG. 1
illustrates a prior art signal transition accelerating bus driver. The prior art signal transition accelerating bus driver is broken down into an output driver
1
, a gate circuit
2
and a signal transition accelerator
3
. A p-channel enhancement type field effect transistor Qp
1
and an n-channel enhancement type field effect transistor Qn
1
are connected in series between a high level line
4
and a low level line
5
, and the series combination of the p-channel enhancement type field effect transistor Qp
1
and the n-channel enhancement type field effect transistor Qn
1
serves as the output driver
1
. The p-channel enhancement type field effect transistor Qp
1
and the n-channel enhancement type field effect transistor Qn
1
complementarily turn on and off, and supply the high level or the low level to a bus line
6
.
The gate circuit
2
includes two transfer gates
7
/
8
and an inverter
9
. The transfer gates
7
and
8
are connected between a data line
10
and the gate electrodes of the field effect transistors Qp
1
/Qn
1
. An enable signal line
11
is connected to the inverter
9
and the first control nodes of the transfer gates
7
/
8
, and the inverter
9
is connected to the second control nodes of the transfer gates
7
/
8
. The enable signal line
11
propagates an enable signal EBL
1
to the first control nodes of the transfer gates
7
/
8
, and the inverter
9
supplies the inverted signal CEBL
1
of the enable signal EBL
1
to the second control nodes of the transfer gates
7
/
8
. When the enable signal EBL
1
is in the high level, the transfer gates
7
/
8
turn on, and a data signal Sin is transferred through the transfer gates
7
/
8
to the gate electrodes of the field effect transistors Qp
1
/Qn
1
.
The signal transition accelerator
3
includes a NAND gate
12
, a NOR gate
13
, delay circuits
14
/
15
and transfer gates
16
/
17
. The NAND gate
12
has two input nodes one of which is directly connected to the bus line
6
and the other of which is connected through the delay circuit
14
to the bus line
6
. Similarly, the NOR gate
13
has two input nodes one of which is directly connected to the bus line
6
and the other of which is connected through the delay circuit
15
to the bus line
6
. The output node of the NAND gate
12
is connected through the transfer gate
16
to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
, and the output node of the NOR gate
13
is connected through the transfer gate
17
to the gate electrode of the n-channel enhancement type field effect transistor Qn
1
. Each of the delay circuits
14
/
15
is implemented by an odd number of inverters connected in series, and both delay circuits
14
/
15
introduce a predetermined delay time into the propagation of a potential level on the bus line
6
. The potential level on the bus line
6
is propagated to the other end of the bus line
6
as a data signal Sout, and returns to the signal transition accelerator
3
as a bus status signal BS
1
. The delay circuits
14
/
15
supply an inverted signal CBS
1
to the other input node of the NAND gate
12
and the other input node of the NOR gate
13
. The NAND gate
12
and the NOR gate
13
offer a feedback loop to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
or the gate electrode of the n-channel enhancement type field effect transistor Qn
1
depending upon the voltage level of the bus status signal BS
1
. The inverter
9
supplies the inverted signal CEBL
1
to the first control nodes of the transfer gates
16
/
17
, and the enable signal line
11
supplies the enable signal EBL
1
to the second control nodes of the transfer gates
16
/
17
. When the enable signal EBL
1
is in the low level, the transfer gates
16
/
17
turn on, and the NAND gate
12
and the NOR ate
13
are connected through the transfer gate
16
to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
and through the transfer gate
17
to the gate electrode of the n-channel enhancement type field effect transistor Qn
1
. Thus, one of the gate circuit
2
and the signal transition accelerator
3
drives the output driver
1
depending upon the voltage level of the enable signal EBL
1
.
Description is firstly made on the driving operation on the bus line
6
in response to the data signal Sin. The data signal Sin and the data signal Sout are assumed to be in the high level and in the low level, respectively. Accordingly, the bus status signal BS
1
and the inverted signal CBS
1
is in the low level and in the high level, respectively.
The enable signal EBL
1
is firstly changed to the high level. The enable signal EBL
1
causes the transfer gates
7
/
8
and the transfer gates
16
/
17
to turn on and off, respectively. The data signal Sin is changed from the high level to the low level, and the potential change is transferred to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
and the gate electrode of the n-channel enhancement type field effect transistor Qn
1
. The data signal Sin gives rise to decrease the potential level at the gate electrode of the p-channel enhancement type field effect transistor Qp
1
and the gate electrode of the n-channel enhancement type field effect transistor Qn
1
. The p-channel enhancement type field effect transistor Qp
1
is varied toward the on-state, and the n-channel enhancement type field
Foley & Lardner
Lam Tuan T.
NEC Corporation
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