Programmable supervisory circuit and applications therefor

Details Programmable supervisory circuit and applications therefor Programmable supervisory circuit and applications therefor

1999-05-26

2001-03-20

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Determining machine or apparatus operating time or...

C377S045000, C377S054000

Reexamination Certificate

active

06205197

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to supervisory circuits for the measurement of low frequency signals and control of power supplies.
BACKGROUND OF THE INVENTION
Electrical measurement metering in power management has been traditionally carried out by analog devices while the electronics industry has been basically converted from analog devices to digital devices primarily computers and other electronic digital apparatus. In keeping with the development of the electronic field it is important that electronic devices such as power management devices be reduced to very small size but still maintain increased flexibility to improve turnaround time in manufacturing so that a basic circuit design can be used in many different devices with only minor modification or reprogramming at the most to fulfill the new function or provide the new voltage or power levels desired.
The need for reliable power supplies has become increasingly important as circuit densities and hence functionality of the various systems powered by these power supplies continue to rise. Unforeseen failure of power supplies in a computer system, for example would be catastrophic, as it can result in the loss of valuable data. As a result, constant supervision or monitoring of the power supply is required and this has made it necessary to include specialized power supervisory circuits within such systems. These supervisory circuits keep the over all system informed about the integrity of the power supply and hence allows for the safe shutdown of the dependent systems in case this integrity is breached.
Generally, supervisory circuits monitor the voltage or current levels of analog voltages or currents and inform the system on whether the signals are within the allowed range of operation. The operating range is fairly large (typically +/−10% of a pre-specified value) and hence, the resolution required to monitor the signal is not too demanding with a +/−2% full-scale resolution being sufficient. Furthermore, the monitored signals have low bandwidths since they are usually the dc output voltage (current) or ac-line input voltage (current) of the power supply. A supervisory circuit, however, may be required to monitor a number of signals simultaneously as a mixed analog-digital system may operate off a number of different voltage levels. Existing power-supervisory applications specific integrated circuits (PS-ASIC) are primarily analog in nature and function sufficiently well in this context. These PS-ASICs, however, are found to be inflexible to changes in component tolerance values that occur during the manufacturing process and are fixed in their signal processing operations once they are set into the product. It would be advantageous therefore to have a PS-ASIC that would accommodate drifts in threshold values due to aging, product upgrades during the lifetime of a product, and alteration of the signal processing capabilities of the PS-ASIC.
Such a PS-ASIC would be “reconfigurable” or field upgradeable and also make possible the use of a single PS-ASIC in a wide range of similar products thereby reducing development costs and time to market.
Until recently, analog based circuit techniques were used for signal processing. These circuits were implemented in bipolar technology and required the use of accurate voltage and current sources as well as precision resistor divider networks for every parametric threshold detection routine used. This was area intensive and due to the drifts that occurred in the references it was also found to be prone to failure in terms of meeting operating specifications. Furthermore, the advent of switched-mode power supplies introduced the ASIC to noisier operating environments making it even more prone to false threshold detection problems. Masking times for threshold faults were achieved by the use of external components (to set RC time constants) which made the PS-ASIC once again susceptible to component tolerance problems. As far as more complex computation were concerned, they all basically relied on obtaining the average time that a waveform (such as the ac line voltage) exceeded a certain threshold value before the resulting average would trip a parametric test. Hence, the computational complexity of these circuits was limited. Finally, the ASIC was fixed in terms of its application to a specific product and hence was not flexible to operate on updated specifications on the same product or other products. These problems have thus made the use of present implementation techniques unattractive.
Switched capacitor circuit techniques make it possible to design programmable mixed analog-digital circuits. For example, a “programmable capacitor array” (PCA) used in an amplifier feedback can result in programmable gains that are controlled by digital co-efficients. PCA's can be used in comparator circuits to obtain programmable trip points by distributing the charge in the PCA to attain the desired threshold voltage. This technique can give a fair degree of programmability in terms of some basic signal processing. However, using PCAs as the primary implementation technique can be expensive in terms of an ASIC layout. For example, an eight bit resolution would require a capacitance spread, (Cmax/Cmin) of 256. Since very small capacitors are undesirable due to increased noise (kT/C noise) and mask resolution inaccuracies and in addition need to be at least an order of magnitude greater than the parasitic capacitance within the circuit (the gate-to-source capacitance of a minimum size CMOS transistor in a typical 1.2 micro-meters CMOS process is 20 Femtoferads (fF)) one is limited in the maximum value of capacitance chosen. For a Cmin of 200 fF, a Cmax/Cmin of 256 would give a Cmax of 51 pF. Given that in a typical 1.2 micro-meter CMOS process, 1 pF occupies approximately 1290 micro-meter
2
this makes Cmax alone occupy 66,000 micro-meters
2
(approximately 102 mil
2
). One can see that area requirements may become quite demanding for an implementation that requires a number of such switched capacitor configurations.
U.S. Pat. No. 5,345,409 makes use of digital signal processors (DSPs) and is incorporated herein by reference. Digital signal processors have gained widespread use in a number of applications including power monitoring as can be seen by the above reference. They are capable of computationally intensive tasks and are programmable by software. The reference discloses a programmable power metering ASIC comprised of a mixed analog-digital circuit that uses a customized DSP for computations. Six Delta-Sigma analog to digital converters are used to provide an oversampled serial bit-stream of information from the six source signals (three in voltage mode and three in current mode). This information is low pass filtered and decimated using digital filtering techniques. The resulting output is fed to the DSP which has two programmable processors that are used to execute calibration and computing operations using the algorithms stored in and off-chip PROM. This allows the ASIC to compute the RMS values, real and apparent power consumptions and power factor rating of the source signals. The final readings are measured to give an absolute accuracy of 0.04% when using the calibration coefficients. The performance of this implementation comes at the expense of silicon die area. The ASIC corresponding to the structure disclosed in the reference occupies about 6.4 mm×7.1 mm in 1.5 micro-meter CMOS technology (most of which is occupied by the DSP) in order to monitor six signals.
One of the objectives of the present invention is to provide sufficient signal processing capability while minimizing the amount of silicon die area required in order to reduce cost and still provide the necessary function.
The invention described herein provides a moderately accurate (less than 2% full-scale error) programmable supervisory circuit that can monitor a number of critical low frequency signals in a complex power supply by applying stochastic and pulse density bas

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