Radiation imagery chemistry: process – composition – or product th – Electric or magnetic imagery – e.g. – xerography,... – Post imaging process – finishing – or perfecting composition...
Reexamination Certificate
2000-02-11
2001-05-08
Elms, Richard (Department: 2824)
Radiation imagery chemistry: process, composition, or product th
Electric or magnetic imagery, e.g., xerography,...
Post imaging process, finishing, or perfecting composition...
C438S117000, C438S118000
Reexamination Certificate
active
06228548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates generally to multichip semiconductor packages and particularly relates to an improved semiconductor package having a plurality of semiconductor chips fabricated as a singular coextensive substrate and to its method of making.
2. The Relevant Technology
Multichip packaging is one of the fastest growing disciplines in the chip packaging industry. Initially, the multichip package came into existence for applications requiring numerous and varied circuits configured into a least amount of space, such as with mainframes and supercomputers. Since then, multichip packages have transcended traditional boundaries and moved into conventional single-chip applications because they characteristically possess reduced weight and size per each circuit, increased reliability and increased electrical performance. As such, multichip packages are now regularly employed in consumer electronics, medical and avionic devices, and in the automotive and aerospace industries. Multichip packages also find particular usefulness in telecommunication applications because of their high bandwidth performance.
In general, conventional multichip packages are available in one of two varieties. One has two or more bare chips bonded directly to a multichip substrate and the other, the most commercially predominant package, having two or more pre-packaged single-chips, in their respective single-chip carriers and bonded to a multichip substrate. Although the former variety enjoys advantages over the latter, both varieties remain bound by single-chip constraints because of their dependence upon either a bare, or packaged, single-chip. As such, both varieties frequently share common problems with their single-chip counterparts.
For example, in response to an industry-wide demand for high lead counts and small “footprints,” i.e., the arrangement of electrical contacts on the printed circuit board to which the chip package is ultimately connected, single-chip packages became available in Ball Grid Array (BGA), “flip-chip” and “chip-scale” packages. The problem, however, is that these singular-chip packages have external electrodes, which can be solder balls, that are directly attached to contacts on the surface of the semiconductor chip. As semiconductor chips are continually reduced in size, the arrangement of the external electrodes must also be continually reconfigured into a correspondingly smaller size. In turn, the footprint on the printed circuit board must also be continually reconfigured. This problem is even further amplified with multichip packages because footprint reconfiguration also needs to occur on the multichip substrate itself to which the single-chip packages are attached. It is, therefore, desirous to eliminate the continual reconfiguring of the footprint of the multichip package and the rearrangement of the multichip substrate.
In a separate and distinct discipline, Wafer Scale Integration (WSI) techniques have been used to fabricate various other multichip arrangements. Yet WSI often utilizes 800, or more, semiconductor chips as a single multichip which, in effect, is too cumbersome, if not prohibitive, to encapsulate into a package format. The large size is also inefficient for applications requiring relatively few semiconductor chips, around 64 or less, because of the high wiring density used in WSI wirebonding operations and the surplus unneeded chips. Effective testing of each individual chip with WSI is also problematic because of the large number of chips. Additionally, WSI techniques frequently require expensive photolithography equipment, not typically utilized with single-chip packages, to transfer a circuit image onto a multichip substrate.
A need exists for a multichip package that overcomes the foregoing problems.
SUMMARY OF THE INVENTION
In accordance with the invention as embodied and broadly described herein, a novel multichip semiconductor package, and method of making, is provided that has a plurality of semiconductor chips fabricated in electrical isolation, one from another, as a singular coextensive semiconductor substrate useful for numerous and varied semiconductor chip applications. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. As such, silicon on insulator and silicon on sapphire are within the definition of substrate.
Once fabricated, instead of being singulated into a plurality of single-chip packages, the semiconductor chips are kept integrally on the substrate. The semiconductor chips, which are electrically isolated one from another, are then wired so as to be electrically connected together to form a larger circuit, such as to expand a memory circuit, and then encapsulated and processed into a single, multichip package.
In a preferred embodiment, a multichip package has a plurality of electrically isolated semiconductor chips integrally formed on a unitary semiconductor substrate. A plurality of conductive leads electrically connect the electrically isolated semiconductor chips. A compound substantially encapsulates at least a portion of the semiconductor substrate, and a plurality of electrodes extend through the compound to make contact with the conductive leads.
In another preferred embodiment, a multichip semiconductor package includes a plurality of electrically isolated semiconductor chips that are integrally formed on a unitary semiconductor substrate, each semiconductor chip having an active device formed thereon. The multichip semiconductor package also includes a plurality of bond pads, each bond pad being electrically connected one per each active device. A plurality of conductive leads electrically connect the electrically isolated semiconductor chips, where each conductive lead is electrically connected one per each bond pad. A compound substantially encapsulates at least a portion of the semiconductor substrate, the bond pads, and the conductive leads. There are also a plurality of solder balls, where each solder ball extends through the compound to make contact with a respective one of the conductive leads.
In yet another preferred embodiment, the common signals of the plurality of semiconductor chips are bussed in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a Printed Wiring Board (PWB). The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the electrode in contact therewith. The electrode contacts the conductive lead through an opening formed in the encapsulant that surrounds the substrate. The extended portions of each conductive lead are staggered with respect to the extended portion of the conductive lead in the same, or juxtaposed, pair set. In this manner, multiple electrodes are available for close proximity positioning while, simultaneously, avoiding electrical shorts amongst the pair sets.
In an alternate embodiment, the conductive leads extend beyond the encapsulant to facilitate testing or improve manageability of the package during the manufacturing process. The conductive leads, after the testing or manufacturing, may then be sheared flush to avoid mechanical interferences between the external circuit, i.e., the PWB, or to create a stronger and thicker multichip package.
A method of making the inventive multichip package includes providing a unitary semiconductor substrate and integrally forming a plurality of electrically isolated semiconductor chips on the unitary semiconductor substrate. There is the
Brooks Jerry M.
King Jerold L.
Elms Richard
Lebentritt Michael S.
Micro)n Technology, Inc.
Workman & Nydegger & Seeley
LandOfFree
Method of making a multichip semiconductor package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a multichip semiconductor package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a multichip semiconductor package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2475142