Method of forming a CMOS image sensor

Details Method of forming a CMOS image sensor Method of forming a CMOS image sensor

1999-08-23

2001-09-11

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S073000, C438S200000, C257S461000, C257S463000

Reexamination Certificate

active

06287886

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a complementary metal-oxide-semiconductor (CMOS) image sensor, and more particularly, to a method of forming an improved photo-diode sensor of an image sensor.
2. Description of the Prior Art
Please refer to FIG.
1
and FIG.
2
.
FIG. 1
is a top-view diagram of an prior art image sensor on a semiconductor wafer
10
.
FIG. 2
is a cross sectional diagram along line
2
—
2
of the semiconductor wafer
10
shown in
FIG. 1. A
CMOS image sensor comprises three NMOS transistors used as a reset MOS, a current source follower and a raw selector, respectively, and a photo-diode sensor for sensing the photo-intensity. As shown in FIG.
1
and
FIG. 2
, the image sensor is formed on a semiconductor wafer
10
which is covered with a positive-type (P-type) substrate
12
. The surface of the semiconductor wafer
10
comprises a negative-channel (N-channel) area
30
for forming three negative-type MOS (NMOS) transistors and a sensor area
32
for forming a photo-diode sensor. The NMOS transistors in the N-channel area
30
are formed by using a conventional lightly doped drain (LDD) process. In the conventional LDD process, first, a P-type well
13
, N-type well, at least one field oxide layer
14
and a gate electrode
16
comprising a conductive layer
18
are formed sequentially. Then, a LDD layers
20
is formed by using an ion-implantation process. Next, spacers
22
are formed. Finally, a heavy doped drain (HDD) layer
24
is formed by using another ion-implantation process with arsenic (As) as the major dopant at a dopant concentration at about 10
19
to 10
20
cm
−3
so as to complete the NMOS transistors. At the same time, a HDD layer
24
is also formed in the sensor area
32
wherein the HDD layer
24
and the P-type well
13
form a PN junction that functions as a photo-diode sensor.
The HDD layer
24
of the photo-diode sensor and the HDD layer
24
of the NMOS transistors are formed at the same time. That is the HDD layer
24
with heavy As forms one side of the photo-diode sensor. In results, there are many shortcomings in the characteristics of the photo-diode sensor, for examples:
1. The atomic size off As is bigger and the dopant concentration is heavier, so the silicon crystal structure within the surface of the sensor area is destroyed severely which leads to an increase in the leakage current of the PN junction, and an increase in the leakage current (also called dark current) of the PN junction when the photo-diode sensor does not accept light. This will increase the noise of the image sensor and decrease the resolution of the image sensor.
2. The width of the depletion region of the PN junction formed with the HDD layer
24
is narrower which leads to a smaller real active region of the sensor area. This will decrease the leakage current (also called photo-current) of the PN junction when the photo-diode sensor accepts light. Therefore, the sensed photo-signal is smaller and the photo-sensibility is worse.
3. The lifetime of charge carriers (also called photo-charges) simulated in the HDD layer
24
caused by accepting light will decay severely. That is the recombination rate of the photo-charges increases as the dopant concentration of the HDD layer
24
increases which leads to a decrease in the generated current after the acceptance of light. Especially, when a short-wave light such as cyan-light irradiates the semiconductor wafer, the skin depth of the semiconductor wafer is shallower. So the sensitivity to the short-wave light will be much worse as the recombination rate of the photo-charges increases.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming an image sensor that can separate the formation of a photo-diode sensor from the formation of a NMOS transistor so as to improve the characteristics of the photodiode sensor.
In a preferred embodiment, the present invention provides a method of forming a complimentary metal-oxide-semiconductor (CMOS) image sensor, the image sensor being formed in a predetermined region of a semiconductor wafer which is covered with a positive-type (P-type) substrate and comprises at least one negative-channel (N-channel) area for forming one negative-type MOS (NMOS) transistor and a sensor area for forming a photo-diode sensor, the method comprising the following steps:
forming at least one gate electrode in the N-channel area;
performing a first ion-implantation process to form a lightly doped drain (LDD) layer in predetermined areas on the surface of the P-type substrate in the N-channel area next to the gate electrode;
performing a second ion-implantation process to form a heavy doped drain (HDD) layer in another predetermined area on the surface of the substrate in the N-channel area next to the LDD; and
performing a third ion-implantation process to form a doped layer with phosphorus as the major dopant on the surface of the substrate in the sensor area;
wherein the dopant concentration of the HDD layer is heavier than that of the LDD layer, and the doped layer in the sensor area and the P-type substrate under the doped layer form a PN junction that functions as a photo-diode sensor.
It is an advantage of the present invention that the destruction issue of the surface crystal within the sensor area can be improved. In addition, the dark-current in the sensor area can be decreased when the photo-diode sensor does not accept light and the photo-current in the sensor area can be increased when the photo-diode sensor accepts light so as to increase the signal to noise ratio (S/N).
This and other objective of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 4107722 (1978-08-01), Chamberlain
patent: 5430321 (1995-07-01), Effelsberg
patent: 5461425 (1995-10-01), Fowler et al.
patent: 5982011 (1999-11-01), Kalnitsky et al.
patent: 6051857 (2000-04-01), Milda
patent: 6071826 (2000-06-01), Cho et al.
patent: 6084259 (2000-07-01), Kwon et al.
patent: 6147372 (2000-11-01), Yang et al.

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