Coating processes – With pretreatment of the base – Preapplied reactant or reaction promoter or hardener
Reexamination Certificate
1995-12-15
2001-07-17
Talbot, Brian K. (Department: 1762)
Coating processes
With pretreatment of the base
Preapplied reactant or reaction promoter or hardener
C427S098300, C427S307000, C427S437000, C427S443100, C216S104000
Reexamination Certificate
active
06261637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electroless metal plating on metallic surfaces and, in particular, to an electroless metal plating process for forming metallic circuits on silicon wafers in which the wafers have metallic circuit patterns thereon comprising a metallic barrier layer between the wafer substrate and the plated metal.
2. Description of Related Art
In the fabrication of integrated circuits on silicon wafers a series of steps are used to make the finished wafer product. In part of the fabrication process, the wafer is coated with a layer of silicon dioxide (SiO
2
) and the SiO
2
or suitable dielectric is etched to form vias or circuit paths on the wafer which are essentially openings in the SiO
2
layer which extend to the silicon layer. The circuit paths are then filled with a conductive metal to form the completed circuit. As is well known, integrated circuit manufacture is very exacting and difficult since the process must be highly reliable and produce wafers having essentially zero defects.
Present wafer metallization schemes use sputtered or evaporated Al-Cu alloys over a previously applied TiW or other suitable barrier/adhesion layer in the opening to fill the opening and complete the circuit. This technology presents some serious drawbacks in terms of its ability to produce circuitry less than 2-2.5 microns line width and to fill the via completely for vias having a height to width aspect ratio greater than 1. At high aspect ratios seams and voids resulting from poor filling not only yield electrical discontinuity and a high via resistance but also invite entrapment of contaminates in subsequent processing steps that in turn often lead to reliability problems. The present metallization schemes try to avoid these problems and use chemical vapor deposition (CVD) or sputtered Al-Cu as the circuit metal but deposition of metals such as aluminum involves many difficulties and requires significant care. Use of directional sputtering has also been investigated but is extremely difficult to control especially at small dimensions and high aspect ratios.
It is desirable to use metals such as nickel or preferably copper for metallization of the wafer because of their electrical properties but these metals and in particular copper have a number of drawbacks, such as a tendency to diffuse through a metal barrier or adhesion layer into the silicon. It is also difficult to etch copper to produce the desired fine line circuit patterns and CVD procedures for depositing copper suffer many complications relating to selectivity and processing temperatures. Accordingly, it is very useful to be able to employ low temperature wet processing techniques such as electroless copper deposition which is relatively economical and easy to use.
A method for the fabrication of electronic devices by electroless copper plating is shown in U.S. Pat. No. 5,308,796 to Feldman et al. and a related article entitled “ELECTROLESS COPPER DEPOSITION ON METALS AND METAL SILICIDES” by a co-inventor, Cecilia Mak, printed in MRS BULLETIN/August 1994, Vol. XIX, No. 8, pages 55-62. Both the patent and publication are incorporated herein by reference. Generally, a thin layer of catalytic material, in particular palladium, is first deposited over a circuit pattern delineated by etched silicon dioxide on a silicon wafer. Annealing converts the palladium adjacent to the silicon surface to Pd
2
Si but the Pd on the SiO
2
remains unreacted. A selective etch is then used to remove the unreacted Pd, leaving behind only the Pd
2
Si at the bottom of the via which overlies the silicon surface. The electroless copper deposition that follows occurs only on the catalytic Pd
2
Si areas. Unfortunately, this method has drawbacks because the whole wafer must be coated with the layer of palladium which palladium must then be selectively etched from all but the desired circuit areas which contain Pd
2
Si. This is a difficult task and remaining palladium on the wafer on other than the desired areas may result in unwanted plating and defective wafers caused by voiding in the vias and other plating problems. The etch solution must then be waste treated to recover the palladium with the inevitable processing and disposal problems.
Another pattern scheme shown in the Mak article, supra, relies on the selective CVD of a thin tungsten film at the bottom of the via. The exposed silicon at the bottom of the via reduces the deposited tungsten hexafluoride to tungsten metal which thin film serves both as a seed layer for subsequent electroless copper deposition and a diffusion barrier layer. It is noted however, that this process has the possibility of forming wormhole-like defects underneath the tungsten layer during the seeding step and that the tungsten film formed solely by silicon reduction may be too porous to be a diffusion barrier layer.
At present, a preferred fabrication technology is to form a tungsten alloy film such as TiW at the bottom of the via by CVD and to metallize the via using CVD technology. One process coats the TiW film with a noble metal typically gold, using CVD techniques with the gold layer serving as both an oxidation protectant and a low ohmic contact for further interconnect metallization. This technique, however, is not entirely satisfactory and it is desired to use more efficient techniques for metallizing vias having a tungsten alloy or other metal barrier layer.
Electroless deposition is the chemical deposition of a metal or mixture of metals over a catalytic surface by chemical reduction and compositions and processes for electroless metal deposition are disclosed in U.S. Pat. No. 3,011,920 incorporated herein by reference. If the substrate to be metal plated is inert—i.e., not catalytic to metal deposition, the conventional process of plating comprises pretreatment to promote cleanliness and adhesion, catalysis of the substrate prior to deposition by treatment with a suitable plating catalyst that renders the surface catalytic to electroless metal deposition followed by a step identified by the art as acceleration.
The catalyst most in commercial use for electroless plating processes comprises the reaction product of a substantial molar excess of stannous tin with palladium ions in a hydrochloric acid solution. The reaction product is believed to be a tin palladium colloid. It is believed that the oxidized stannic tin in combination with unreacted stannous tin and palladium ions form a protective, possibly polymeric, complex for the palladium or palladium-tin alloy while the unreacted stannous ions act as an antioxidant.
An improvement in colloidal tin palladium catalysis is disclosed in U.S. Pat. No. 3,904,792 incorporated herein by reference. In this patent, to provide a catalyst that is less acidic than those disclosed in the aforesaid U.S. Pat. No. 3,011,920, a portion of the hydrochloric acid is replaced by a solution soluble metal halide salt of the acid resulting in a more stable catalyst having a pH that can approach about 3.5.
It is known in the art that using a catalyst formed from the reaction product of stannous tin and noble metal ions, a process sequence would typically include the steps of catalysis of the substrate, acceleration of the catalytic layer, typically with an acid such as fluroboric or perchloric acid and electroless metal deposition. The step of acceleration is known to activate the palladium catalyst, enhance the initiation of the plating reaction and decrease the plating time for total coverage of the part to be plated.
Unfortunately, conventional processes for electroless plating cannot be used for plating silicon wafers because of their lack of selectivity in that the catalysts will catalyze the whole wafer and unless the catalyst is removed from unwanted areas, unwanted plating will occur causing defective parts.
For convenience, the following description will be directed to silicon wafer integrated circuits and tungsten based alloys and in particular TiW alloys used as the metallization barrier layer to be elect
DeLio & Peterson LLC
Enthone-OMI Inc.
Mueller Richard P.
Talbot Brian K.
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