Color palette ram and D/A converter

Details Color palette ram and D/A converter Color palette ram and D/A converter

2000-01-28

2001-05-01

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S138000, C341S145000

Reexamination Certificate

active

06225932

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a color palette RAM and a D/A converter. In particular, it relates to a color palette RAM and a current output type D/A converter for graphics applications.
A schematic circuit diagram of a color palette RAM in the prior art is shown in FIG.
24
. As illustrated in
FIG. 24
, the color palette RAM
10
in the prior art is provided with a RAM
11
for storing color data and an address register
12
that holds an address input via an address input terminal and outputs it to the RAM
11
. The address register
12
holds an input address and outputs it to the RAM
11
at the rise of a clock pulse CLK. Then, at the following rise of the CLK pulse CLK, the RAM
11
outputs color data that corresponds to the address that has been output by the address register
12
.
In addition,
FIG. 25
presents a schematic circuit diagram of a current output type D/A converter for graphics applications in the prior art. It is to be noted that in the example in
FIG. 25
, the D/A converter has a resolution of 4 bits. As illustrated in the figure, 4-bit color data are input via a color data input terminal to the D [0:3] terminal of a data register
23
, and a signal output from the OUT [0:3] terminal of the data register
23
is input to the D [0:3] terminal of a decoder
22
. A decode signal output from the SELECT [0:14] terminal of the decoder
22
is input to the SELECT [0:14] terminal of a current conversion circuit
21
, and the signal output from the AN_OUT terminal of the current conversion circuit
21
constitutes the D/A converter output signal. In addition, a clock pulse CLK is input via the CLK input terminal to the data register
23
and the decoder
22
.
A circuit diagram of the current conversion circuit
21
, which converts input color data to a current for output, is presented in FIG.
26
. As illustrated in
FIG. 26
, a plurality of current output circuits COC, e.g. 15 current output circuits COC, each of which outputs a constant current, are provided in the current conversion circuit
21
, and current output circuits COC are selected with a SELECT signal provided by the decoder
22
in a quantity that corresponds to the input color data, so that the total current output from the current output circuits COC selected by the SELECT signal is output from the AN_OUT terminal of the current conversion circuit
21
to constitute the output signal of the D/A converter.
In addition, a circuit diagram that represents an example of a current output circuit COC is shown in FIG.
27
. As illustrated in
FIG. 27
, the current output circuit COC is provided with a current source
30
for outputting a constant current, which is constituted of a PMOS transistor
30
a
and a PMOS transistor
30
b
whereby a selection is made as to whether the output current from the current source
30
is to be output from the I_OUT terminal or discharged to the ground by using switching elements (a PMOS transistor
31
and a PMOS transistor
32
) based upon the SELECT signal provided by the decoder
22
.
The structure described above is adopted because, when control is implemented to operate/stop the current source
30
based upon the SELECT signal, a certain length of time is required before the output current from the current source
30
becomes stabilized after the current source
30
is switched from the stopped state to the operating state and, in order to operate the D/A converter at high speed, it is therefore necessary that the current source
30
output a constant current at all times.
Next, the operation of the D/A converter illustrated in
FIG. 25
is explained in reference to FIG.
28
. In
FIG. 28
, a timing chart corresponding to the circuit diagram in
FIG. 25
is presented. As illustrated in
FIG. 28
, when color data “0000” are input via the color data input terminal, the data register
23
holds the color data “0000” and outputs them to the decoder
22
at the following rise of the CLK. Then, at the following rise of the CLK, the decoder
22
outputs a SELECT signal for selecting the current output circuits COC in the current conversion circuit
21
based upon the color data output by the data register
23
.
Through this process, when the color data “0000” are input via the color data input terminal, the signal output from the SELECT [0:14] terminal of the decoder
22
is “0000 h,” with the result that no current output circuits COC in the current conversion circuit
21
shown in
FIG. 26
are selected. This sets the level of the current output from the analog output terminal of the D/A converter to 0.
However, when color data “0001” are input via the color data input terminal, the decoder
22
outputs a signal “0001 h,” which corresponds to the color data “0001” from the SELECT [0:14] terminal, resulting in the current output circuit COC [1] in the current conversion circuit
21
being selected, to set the level of the current output from the analog output terminal to 1.
Likewise, when color data “0010” are input, the signal output from the SELECT [0:14] terminal is “0003 h,” resulting in two current output circuits COC, i.e., the current output circuit COC [1] and the current output circuit COC [2], being selected, to set the level of the current output from the analog output terminal to 2.
In addition, when color data “1000” are input, the signal output from the SELECT [0:14] terminal is “00 FFh,” resulting in eight current output circuits COC, i.e., the current output circuits COC [1] through [8], being selected, to set the level of the current output from the analog output terminal to 8.
Furthermore, when color data “1111” are input, the signal output from the SELECT [0:14] terminal is “7 FFFh,” resulting in all the current output circuits COC being selected, to set the level of the current output from the analog output terminal to
15
.
It is to be noted that, since the operation of the current sources
30
in the unselected current output circuits COC do not stop, as explained earlier, the output currents from the current sources
30
at the unselected current output circuits COC are discharged to the ground.
As explained above, in the current output type D/A converter in the prior art, the data register
23
, the decoder
22
and the current conversion circuit
21
are provided, with the data register
23
holding input color data to output it to the decoder
22
at the rise of the CLK pulse. Then, at the following rise of the CLK pulse, the decoder
22
outputs the SELECT signal to the current conversion circuit
21
in correspondence to the color data output from the data register
23
, and the current conversion circuit
21
, in turn, outputs a current based upon the SELECT signal provided by the decoder
22
.
However, in the color palette RAM in the prior art structured as described above, since a clock pulse is supplied to the RAM
1
even when a single address is input continuously with the consequence that the output data from the color palette RAM do not change, operations such as precharge are performed continuously. Performing these operations continuously causes an increase in power consumption, which works against the need for reduced power consumption.
In addition, in the current output type D/A converter structured as described above, in which the currents are output from the I_OUT terminals of the current output circuits COC in the current conversion circuit
21
that have been selected by the decoder
22
, the output currents from unselected current output circuits COC are discharged to the ground with currents flowing constantly from the current source
30
in all the current output circuits COC regardless of input color data. Thus, this operation also causes an increase in power consumption which works against the need for reduced power consumption.
OBJECTS AND SUMMARY OF THE INVENTION
An object of the present invention, which has been completed by addressing the

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