Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
1998-07-30
2001-05-22
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S571000, C257S578000, C257S580000, C257S582000, C257S586000, C257S592000
Reexamination Certificate
active
06236071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to transistors, and particularly to a Heterojunction Bipolar Transistor (HBT) having a novel layout and an emitter having more than one feed point.
2. Background Art
The global wireless market is rapidly expanding as people demand products that increase the ability to communicate freely without time and place restrictions. These products includes the very popular cellular telephones that employ either analog or digital technology. Cellular telephones utilize a transmitter to transmit data to a local base-station that in turn forwards the data to another base-station or the intended party. An important component in the transmitter and in other wireless communication systems is the power amplifier. The design of power amplifiers employs power transistors. A common power transistor is the Heterojunction Bipolar Transistor (HBT).
FIG. 1
illustrates a layout of a conventional HBT
1
having a first section
2
(also referred to as an “active” area) with a collector terminal
7
, a second section
3
with a base terminal
5
, and a third section
4
with an emitter terminal
6
. The first section
2
includes three rectangular collector contacts
10
and two rectangular base pedestals
11
. Each base pedestal
11
includes a rectangular base contact
12
and a rectangular emitter
13
. Emitter contacts (not shown) are deposited over the emitters
13
.
A base ballast resistor
8
having a layout with two rectangular areas is coupled between a base terminal
5
and base contact
12
. An emitter ballast resistor
9
having a layout with two rectangular areas includes a first end that is coupled to emitter terminal
6
and a second end that is coupled to the emitter contact.
FIG. 2
illustrates a cross sectional view of transistor
1
of FIG.
1
through line
2
—
2
. This sectional view further illustrates that there are two separate base pedestals
11
, two separate base contacts
12
, two separate emitters
13
, and three separate collector contacts
10
for each transistor
1
. A first metal layer
14
and a second metal layer
15
are deposited and selectively etched away so as to contact portions of transistor
1
, such as collector contact
10
, base contact
12
, and emitter
13
.
Unfortunately, these conventional HBTs suffer from the following disadvantages:
1
) large area;
2
) susceptibility to emitter failure; and
3
) poor electrical performance.
LARGE AREA
Since the area occupied by power transistors in a power amplifier is a significant portion of the total die area for a power amplifier, reducing the area of the power transistors is desirable since this can substantially reduce the total die area occupied by the power amplifier. As is well-known by those skilled in the art, a reduction of the total die area for a circuit would reduce the costs to manufacture the circuit and would also increase integration (i.e., the number of circuit elements that can be integrated into a circuit design).
However, the ability to reduce the area of circuits is hindered by heat concerns as systems migrate to lower voltages. As the voltage of the system decreases, designers are forced to make the transistors larger to accommodate a fixed power requirement (i.e., P=VI, where P is the power, V is the voltage, and I is the current). If V decreases, such as in a low operating voltage environment, then I must increase to keep P constant. However, an increase in I is accomplished through a larger transistor area and in particular a larger emitter area. Therefore, conventional power transistors
1
that are designed for use in low voltage systems have layouts with large area requirements in order to handle the high current levels.
Consequently, it is a challenge to design transistors that can handle the current requirements of a low operating voltage system while simultaneously maintaining or shrinking the layout area of the transistor.
SUSCEPTIBILITY TO EMITTER FAILURE
Moreover, in conventional power transistors
1
, the current density in the emitters
13
is uneven. In other words, there is a low current density at a first end
13
A of emitter
13
while there is a high current density at a second end
13
B of emitter
13
. Since a high current density exposes the second end
13
B of the emitter
13
to extremely high temperatures, the transistor
1
is susceptible to failure stemming from emitter
13
failure (e.g., emitter burn-out).
POOR ELECTRICAL PERFORMANCE
Conventional power transistors
1
also suffer from a high base-to-collector capacitance that impairs electrical performance of the transistor I and thereby adversely affects any circuit that utilizes the transistor
1
. In a rectangular layout, the base pedestals
11
and the collector contacts
10
are capacitively coupled causing feedback between the collector and base areas. Furthermore, since the base-to-collector capacitance is proportional to the base pedestal areas, the large base pedestal area of conventional power transistors
1
increases the base to collector capacitance, thereby decreasing performance.
Accordingly, there remains a need for a transistor that occupies less area and is suitable for low operating voltages, while maintaining performance and reliability of the transistor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a transistor having a compact layout.
It is a further object of the present invention to provide a transistor that is suitable for low operating voltage environments while maintaining performance and reliability.
It is another object of the present invention to provide a transistor having an emitter layout that increases emitter reliability.
It is yet another object of the present invention to provide a transistor having a base pedestal layout that reduces the base-to-collector capacitance.
It is a further object of the present invention to provide a transistor having a collector contact and emitter layout that reduces the collector-to-emitter resistance.
It is another object of the present invention to provide a transistor having a layout that provides for heat shunting within a transistor cell.
It is yet another object of the present invention to provide a transistor having a layout that provides for heat shunting across adjacent transistor cells.
In order to accomplish the objects of the present invention, a transistor with a novel compact layout is provided. In a first embodiment, the novel layout includes an emitter formed within a first section of a transistor having a track with a first feed point and a second feed point whereby current flows through both the first feed point and the second feed point. The transistor includes a base terminal, a collector terminal, and an emitter terminal. When in operation, current flows from the collector terminal to the emitter terminal based on the amount of current provided to the base terminal. The transistor includes a sub-collector layer formed on a substrate. A collector layer is formed on the sub-collector layer. A base pedestal is formed on the collector layer. A base contact for coupling to the base terminal and an emitter are formed on the base pedestal. An emitter contact for coupling to the emitter terminal is formed on the emitter. A collector terminal for coupling to the collector contact is deposited in a trench that is formed in the collector layer and the sub-collector layer. A base ballast resistor is provided in the second section of the transitor, and an emitter ballast resistor is provided in the third section of the transitor.
In an alternative embodiment, the intrinsic (first) section and the third section remain essentially the same as the first embodiment. The second section features the following differences. A first dielectric disposed between an inactive region and layers formed on the first dielectric layer includes windows so that the first metal layer can contact the inactive region. Also, a second metal layer includes a portion that bridges the legs of the first metal layer. In the first section, the
Conexant Systems Inc.
Loke Steven
Thomas Kayden Horstemeyer & Risley, L.L.P.
LandOfFree
Transistor having a novel layout and an emitter having more... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor having a novel layout and an emitter having more..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor having a novel layout and an emitter having more... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2474414