Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-01-15
2001-06-05
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S723000, C257S777000
Reexamination Certificate
active
06242285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stacked package of semiconductor package units and a manufacturing method therefor in which a number of semiconductor package units can be stacked, and more particularly, to a stacked package of semiconductor package units and a stacking method therefor, in which a number of semiconductor packages can be efficiently stacked, by directly connecting respective leads of upper and lower semiconductor packages forming the stacked package with one another, without using separate means for connecting respective leads of the semiconductor packages with one another.
2. Description of the Related Art
Most of devices include semiconductor packages performing a variety of functions to form an circuit. In general, the semiconductor packages are surface-mounted on a printed circuit board (PCB) by the piece. However, since various devices become compact with the development of technologies, and a demand for miniaturization also increases, technologies of mounting a number of components on a unit surface, among which a stack packaging technology for mounting a number of semiconductor packages on an identical area and improving an efficiency of mounting the semiconductor packages is particularly swiftly developed and approaches to an practical stage.
A conventional technology for a stacked package will be described with reference to
FIGS. 1A and 1B
.
FIG. 1A
is a perspective view of a conventional stacked package and
FIG. 1B
is a cross-sectional view taken along a line r-r′ of FIG.
1
A.
As depicted, a conventional stacked package is formed by electrical connection between a number of leads (which are called pins) of respective semiconductor packages IC
A
and IC
B
to be connected to each other using separate auxiliary means which are called headers H
1
-H
20
in which two semiconductor packages IC
A
and IC
B
are located in the upper portion and the lower portion, respectively, that is, one on top of the other so that the respective leads face one another. For the operation of the respective semiconductor packages IC
A
and IC
B
forming a stacked package, when a connection between leads P
19
A
and P
19
B
of the semiconductor packages IC
A
and IC
B
should be blocked like a H
19
header, an intermediate portion of the header H
19
is cut and the remaining portion of the header H
19
transverses the upper portion of the stacked package, to be connected to opposite desired leads. By doing so, in the case that a semiconductor package unit is a 64M synchronous dynamic random access memory (SDRAM), a stacked package having a capacity of 128M SDRAM is formed on the similar mounting area using two semiconductor packages IC
A
and IC
B
.
However, the above conventional stacked package should contain a number of headers H
1
-H
20
as many as the number corresponding to a number of leads for electrical connection between the corresponding leads, and removes an inter-lead connection portion in the H
19
header for electrical disconnection between particular leads. As a pitch between leads, that is, an interval between adjacent two leads becomes narrow with the development of technology, it is difficult and inconvenient to form a stacked package. Moreover, there is a problem that a parasitic capacitance and impedance increase due to headers, so that such an increase influences an operational frequency of the stacked package.
Also, since headers are attached at the state where leads of the semiconductor packages IC
A
and IC
B
are deformed in shape in the conventional stacked package, as shown in
FIG. 1A
, after being fabricated in the form of a package, the width of the completed stack package becomes larger than that of a package unit, to thereby cause a mounting area to increase.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a stacked package of semiconductor package units via direct connection between leads in which a number of semiconductor packages can be efficiently stacked, by directly connecting between predetermined leads of semiconductor packages forming the stacked package, so as to be stacked, without using separate means such as conventional headers for connecting between respective leads of semiconductor packages, but using semiconductor packages whose connection structure between a CS(Chip Selection) lead having an select-function for selecting the operations of predetermined semiconductor packages internally and externally and an NC(No-Connected) lead among a number of NC leads, is varied.
It is another object of the present invention to provide a stack method for stacking semiconductor package units in which a number of semiconductor packages can be efficiently stacked, by directly connecting between respective leads of semiconductor packages except for predetermined leads, at the state where the leads of the semiconductor package completed in the form of a package are deformed for stacking easily, and simultaneously electrical connection is formed between particular leads, considering a changed state after changing a CS lead connection with respect to an inner die before or after the semiconductor package units have been completed in the form of a package.
To accomplish the above object of the present invention, there is provided a stacked package of semiconductor package units having a first semiconductor package and at least one second semiconductor package stacked on top of the first semiconductor package, the stacked package characterized in that the first semiconductor package comprises a number of first leads having at least one first chip selection lead for connecting the stacked package to an external circuit; and the second semiconductor package comprises a number of second leads having at least one second chip selection lead corresponding to a number of leads of the first semiconductor package, wherein predetermined second leads of the second semiconductor package are directly connected to the first leads of the first semiconductor package while the respective CS leads of the first and second packages being electrically disconnected to each other.
There is also provided a stack method for stacking semiconductor package units through direct connection between leads, the stack method comprising the steps of: (a) fabricating semiconductor packages in the form of a package; (b) deforming a number of leads included in a predetermined number of the semiconductor packages fabricated in step (a), so as to be easily stacked; and (c) directly connecting a number of first leads of the first semiconductor package fabricated in step (a) in correspondence to predetermined second leads of at least one second semiconductor package in which a number of second leads are deformed in step (b).
REFERENCES:
patent: Re. 36229 (1999-06-01), Cady
patent: 4956694 (1990-09-01), Eide
patent: 5138438 (1992-08-01), Masayuki et al.
patent: 5221642 (1993-06-01), Burns
patent: 5236117 (1993-08-01), Roane et al.
patent: 5279029 (1994-01-01), Burns
patent: 5313096 (1994-05-01), Eide
patent: 5332922 (1994-07-01), Oguchi et al.
patent: 5367766 (1994-11-01), Burns et al.
patent: 5369056 (1994-11-01), Burns et al.
patent: 5369058 (1994-11-01), Burns et al.
patent: 5371866 (1994-12-01), Cady
patent: 5377077 (1994-12-01), Burns
patent: 5420751 (1995-05-01), Burns
patent: 5446620 (1995-08-01), Burns et al.
patent: 5448450 (1995-09-01), Burns
patent: 5455740 (1995-10-01), Burns
patent: 5479318 (1995-12-01), Burns
patent: 5484959 (1996-01-01), Burns
patent: 5493476 (1996-02-01), Burns
patent: 5498906 (1996-03-01), Roane et al.
patent: 5499160 (1996-03-01), Burns
patent: 5512783 (1996-04-01), Wakefield
patent: 5528075 (1996-06-01), Burns
patent: 5543664 (1996-08-01), Burns et al.
patent: 5550711 (1996-08-01), Burns et al.
patent: 5552963 (1996-09-01), Burns
patent: 5561591 (1996-10-01), Burns
patent: 5566051 (1996-10-01), Burns
patent: 5572065 (1996-11-01), Burns
patent: 5581121 (1996-12-01), Burns et al.
patent: 5585668 (1996-12-01), Burns
patent: 55860
Berezny Nema
F. Chau & Associates LLP
Nguyen Tuan H.
LandOfFree
Stacked package of semiconductor package units via direct... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked package of semiconductor package units via direct..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked package of semiconductor package units via direct... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2473403