Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-09-28
2001-09-04
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S721000, C438S906000
Reexamination Certificate
active
06284662
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a cobalt silicide layer by use of a tetraethylorthosilicate oxide film as a through oxide film for ion-implantation process.
A self-aligned silicidation or a salicidation technique has been used to form self-aligned silicide layers or salicide layers on surfaces of a polysilicon gate and source and drain regions in order to reduce resistances of not only the gate electrode but also the source and drain diffusion regions. This salicidation technique is applicable to sub-micron devices.
In prior art processes already known, a through oxide film is formed over a silicon substrate with a polysilicon gate in a chemical vapor deposition method by use of SiH
4
based gas. An ion-implantation process is then carried out to selectively form source and drain regions for subsequent rapid thermal anneal for activation of the source and drain regions. Further, the used through oxide film is removed by use of a hydrofluoric acid based solution before a cobalt silicidation process is then carried out to form cobalt silicide layers on surfaces of the polysilicon gate and the source and drain regions. If an SiH
4
based CVD oxide film is used as the through oxide film, then an Si—O based layer is formed over a surface of the substrate by the ion-implantation and subsequent rapid thermal anneal. Such the unnecessary Si—O based layer is, however, removable together with the through oxide film by the wet etching process using the hydrofluoric acid solution, resulting in a clean silicon surface appearing.
In order to have improved throughput, it has been proposed to use a tetraethylorthosilicate oxide film (SiO2) as the through oxide film, wherein the tetraethylorthosilicate oxide film (SiO2) is formed in a low pressure chemical vapor deposition method using tetraethylorthosilicate as a source. Tetraethylorthosilicate will hereinafter be referred to as TEOS. A large amount of carbon toms in the TEOS oxide film, for which reason not only oxygen but also carbon are introduced into the substrate by knock-on. The introduction of ot only oxygen but carbon into the substrate results in a formation of an Si—O—C based layer over the silicon substrate surface by the rapid thermal anneal for the activation to the source and drain regions, wherein the Si—O—C based layer is unremovable by the above wet etching process using the hydrofluoric acid based solution.
This residual Si—O—C based layer causes a problem that oxygen and carbon inhibit cobalt-silicidation reaction between cobalt and silicon atoms. Namely, oxygen and carbon serve as cobalt silicidation inhibitors.
The above problem will be described in more detail with reference to the drawings.
FIG. 1A
is a fragmentary cross sectional elevation view illustrative of a MOS field effect transistor after an ion-implantation process and subsequent rapid thermal anneal for activation to source and drain regions have been carried out.
FIG. 1B
is a fragmentary cross sectional elevation view illustrative of a MOS field effect transistor after a TEOS oxide film has been removed by a wet etching process using a diluted hydrofluoric acid solution.
With reference to
FIG. 1A
, source and drain regions
12
and
14
are selectively provided in a silicon substrate
10
, whereby a channel region is defined between the source and drain regions
12
and
14
. A gate oxide film
18
is formed on the channel region of the silicon substrate
10
. A polysilicon gate electrode
16
is provided on the gate oxide film
18
. Side wall oxide films
20
are also provided on side walls of the polysilicon gate electrode
16
. Under the side wall oxide films
20
, the source and drain regions
12
and
14
are lightly doped regions. A TEOS oxide film
22
as a through oxide film entirely extends on a top surface of the polysilicon gate electrode
16
, and on the side wall oxide films as well as on top surfaces of the source and drain regions
12
and
14
. In the rapid thermal anneal for activation of the source and drain regions
12
and
14
, oxygen and carbon included in the TEOS oxide film are knocked-on and introduced into surface regions of the polysilicon gate electrode
16
, and the source and drain regions
12
and
14
, whereby an Si—O—C based reaction inhibitor layer
24
is formed on the surfaces of the polysilicon gate electrode
16
, and the source and drain regions
12
and
14
.
In order to remove the contaminant on the surface of the TEOS oxide film
22
, a cleaning process is carried out by use of an acid solution such as a sulfate-hydrogen peroxide solution or an ammonium-hydrogen peroxide solution for subsequent wet etching process using a diluted hydrofluoric acid solution with a diluting ratio of 1:100. This wet etching is carried out in order to remove the TEOS oxide film
22
. The cleaning process and the subsequent wet etching process are unable to realize a complete removal of the Si—O—C based reaction inhibitor layer
24
. Namely, the Si—O—C based reaction inhibitor layer
24
resides on the surfaces of the polysilicon gate, and the source and drain regions. Subsequently, a Co film having a thickness of 100 angstroms is deposited on the residual Si—O—C based reaction inhibitor layer
24
by sputtering Co target at a temperature of 400° C., so that a silicidation reaction is caused on an interface between the Co film and the surface of the polysilicon gate electrode and also on interfaces between the Co film and the surfaces of the source and drain regions, whereby a cobalt silicide layer (CoSi
2
) is formed on the surfaces of the polysilicon gate electrode and the source and drain regions. This cobalt silicide layer, however, has a high sheet resistance of about 100 &OHgr;/□. The cobalt silicide layer also has a thickness of not more than 100 angstroms which is much thinner than the intended or necessary thickness in the range of 300-350 angstroms. The higher sheet resistance and the thinner thickness of the actually cobalt silicide layer means that the residual Si—O—C based reaction inhibitor layer
24
inhibits the cobalt silicidation reaction.
In the above circumstances, it had been required to develop a novel method of forming a cobalt silicide layer free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel method of forming a cobalt silicide layer free from the above problems.
It is a further object of the present invention to provide a novel method of forming a cobalt silicide layer without any inhibition to cobalt silicidation reaction after a TEOS oxide layer has been used as a through oxide layer for ion-implantation process.
It is a still further object of the present invention to provide a novel method of forming a cobalt silicide layer having a reduced sheet resistance.
It is yet a further object of the present invention to provide a novel method of causing a cobalt silicidation reaction without any substantive inhibition even after a TEOS oxide layer has been used as a through oxide layer for ion-implantation process.
It is a further more object of the present invention to provide a method of forming a semiconductor device which has a cobalt silicide layer with a reduced sheet resistance.
It is moreover object of the present invention to provide a method of forming a field effect transistor which has a cobalt silicide layer with a reduced sheet resistance.
The present invention provides a method of forming a cobalt silicide layer on a silicon region. The method comprises the steps of: forming a TEOS oxide film on a surface of the silicon region; carrying out an ion-implantation process for implanting ions through the TEOS oxide film into the silicon region; carrying out a heat treatment to activate the ions implanted in the silicon region, whereby a silicidation reaction inhibitor layer is concurrently formed on an interface between the TEOS oxide film and the surface of the silicon region; carrying out a dry etching t
Chen Kin-Chan
NEC Corporation
Utech Benjamin L.
Young & Thompson
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