Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Substrate dicing
Reexamination Certificate
1999-09-07
2001-03-06
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Substrate dicing
Reexamination Certificate
active
06197609
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing semiconductor light emitting devices wherein a light emitting chip is formed by first laminating semiconductor layers including a p-type layer and an n-type layer onto a wafer form substrate and breaking the wafer into individual chips thereafter. More particularly, the present invention relates to a method for manufacturing semiconductor light emitting divice such as blue to yellow semiconductor light emitting devices obtained by laminating gallium nitride based compound semiconductor onto a sapphire substrate, wherein breaking of the wafer into individual chips is performed by dicing a semiconductor layer side, and the number of processes to be performed can be decreased and losses of the wafer can be decreased.
BACKGROUND OF THE INVENTION
Chips of semiconductor light emitting devices (hereinafter referred to as “LED chips”) that generate blue to yellow light of high luminance are conventionally manufactured in the following manner. As shown in
FIG. 3
, there are sequentially formed, through epitaxial growth onto a sapphire substrate
21
, an n-type layer (cladding layer)
23
of e.g. n-type GaN, an active layer (light emitting layer)
24
of e.g. InGaN based compound semiconductor (wherein the ratio of In and Ga may be varied as it similarly applies hereinafter) which is a material whose band gap energy is smaller than that of the cladding layer and which determines the light emitting wavelength, and a p-type layer (cladding layer)
25
of p-type GaN. A p-side electrode 28 is formed onto a surface of the laminated semiconductor layers with a current diffusion layer
27
interposed between, and a part of the laminated semiconductor layers is etched so that an n-side electrode
29
is formed on the exposed surface of the n-type layer
23
. A protecting film
30
of e.g. SiO
2
is further provided on the surface such that the electrodes
28
,
29
are exposed therefrom, and dicing is performed to obtain a dicing groove
31
having a depth of approximately several tens of &mgr;m. After grinding a rear surface of the substrate
21
for thinning the wafer from approximately 350 &mgr;m to assume a thickness of approximately 100 &mgr;m, a scribe line
21
a
is formed from the rear surface of the substrate
21
at boundary line S of the chips by using a diamond cutter or the like, and by applying force to the portion of the scribe line
21
a
, breaking is performed to divide the wafer into individual chips.
Since a sapphire substrate is extremely hard, the depth of the scribe line
21
a
will be a shallow cut of not more than several &mgr;m. It should be noted that an AlGaN based (wherein the ratio of Al and Ga may be varied as it similarly applies hereinafter) compound semiconductor layer may be used on the side of the active layer
23
since n-type layer
23
and p-type layer
25
function to improve confinement effect of carriers. Further, when performing etching of the above-described semiconductor layers to be laminated, portions to be broken are simultaneously etched at the boundary lines S of individual chip to expose the n-type layer
23
whereby easy breaking is made possible.
In case dividing is performed through dicing after a protection film is provided on the surface side of the semiconductor layers in the above-described manner, the protection film
30
may cause chipping at the time of performing dicing such that cracks directed to various directions may be formed on the protection layer
30
by an edge of a dicer so that the yield factor is degraded. In order to solve this problem, it is generally performed that dicing is performed after removing the protection film
30
of portions to be diced, as shown in the sectional view and the plan view of FIG.
3
and
FIG. 4
, respectively. In this case, width A for removing the protection layer is required to be approximately 60 &mgr;m in view of the fact that width W of the dicing groove
31
is approximately 20 &mgr; m, that distance B between the dicing groove
31
and the protection film
30
is at least required to be approximately 15 &mgr;m in view of reliability, and that a positional shift of the dicing groove
31
be approximately 5 &mgr;m.
As explained above, in case dicing is performed after forming a protection film on a surface side of the semiconductor layers, it is presented a drawback that the protection film be damaged to be inferior in reliability and that the yield factor be degraded in case dicing is performed without removing the protection film. On the other hand, in case removal of the protection film at portions to be diced is preliminarily performed, it is required to secure two margins, one for the pattern shift at the time of etching the protection film and the positional shift at the time of dicing, so that intervals between chips need to be kept wider. This will result in a fewer number of chips to be obtained from a wafer though the sizes of the wafers may be identical, and will cause a drawback in that the costs become higher.
SUMMARY OF THE INVENTION
The present invention has been made for solving such problems, and it is a purpose of the present invention to provide a method for manufacturing semiconductor light emitting device wherein breaking (dividing) from a wafer into individual chips through dicing can be performed without etching the protection film and without damaging the protection film.
The manufacturing method for semiconductor light emitting device according to the present invention comprises the steps of
(a) laminating semiconductor layers onto a wafer form substrate which forms a light emitting layer and which includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer,
(b) exposing the second conductivity type semiconductor layer by removing a portion of the laminated semiconductor layers,
(c) forming first and second electrodes on the first conductivity type semiconductor layer that is the surface of the laminated semiconductor layers and on the second conductivity type semiconductor layer that is exposed by removing a part of the laminated semiconductor layers, respectively in an electrically connected manner,
(d) dicing the wafer form substrate with the laminated semiconductor layers at portions to be broken into individual chips extending from a side of the second conductivity type semiconductor layer that is exposed by removing, as to reach the substrate,
(e) providing a protection film on the entire surface of the laminated semiconductor layers in a manner that the first and second electrodes are exposed, and
(f) breaking the wafer form substrate into individual chips by performing dividing at the portions of dicing.
Here, the term “dicing” means to form a cutting groove to assume a certain depth by using a dicer or the like, and “breaking” means to divide the wafer into individual chips by splitting (fracturing) or cutting.
In the above method, the protection film is provided after forming grooves through dicing so that it is not necessary to remove the protection film of the breaking portions through etching, and it will moreover be prevented that the protection film be damaged at the time of performing dicing. Further, no margin for alignment at the time of etching the protection film will be required so that the number of chips to be obtained from a single wafer will be increased.
In case the substrate is made of a sapphire and the laminated semiconductor layers a gallium nitride based compound semiconductor, especially large effects may be achieved since the chip of light emitting device may be easily obtained wherein semiconductor layers are laminated on a sapphire substrate which is generally hard to be broken.
Here, a “gallium nitride based compound semiconductor” refers a semiconductor comprising a compound having Ga of III group elements and N of V group elements wherein a part or all of the Ga of III group elements may be substituted by other III group elements such as Al or In and/or a part of N of the V group elements may be sub
Ito Norikazu
Sonobe Masayuki
Tsutsui Tsuyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Bowers Charles
Christianson Keith
Rohm & Co., Ltd.
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