Operational amplifier

Details Operational amplifier Operational amplifier

1999-09-03

2001-06-12

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000

Reexamination Certificate

active

06246288

ABSTRACT:

FIELD OF THE INVENTION
1. Background of the Invention
The present invention relates to an operational amplifier constituted of a semiconductor integrated circuit comprising, for instance, MOS field effect transistors (hereafter referred to as “FET”) that is provided with a push/pull-type output stage constituted of a complementary MOSFET (hereafter referred to as a “CMOS”) comprising a P-channel MOSFET (hereafter referred to as a “PMOS”) and an N-channel MOSFET (hereafter referred to as a “NMOS”) and the like.
2. Description of the Related Art
FIG. 2
is a circuit diagram presenting a structural example of an operational ampler provided with a push/pull-type output stage in the prior art.
This operational amplifier is provided with a differential stage
1
that amplifies the difference between a negative phase input voltage VIa and a positive phase input voltage VIb and outputs a differential output voltage VA, a level shift stage
2
that shifts the level of the differential output voltage VA with a specific level shift voltage and outputs a level shift output voltage VB and a push/pull-type output stage
3
that outputs an output voltage VO by engaging in an on/off operation using the differential output voltage VA and the level shift output voltage VB.
The differential stage
1
is provided with a negative phase input terminal
1
a
through which the negative phase input voltage VIa is input and a positive phase input terminal
1
b
through which the positive phase input voltage VIb is input, and these input terminals
1
a
and
1
b
are respectively connected to the gates of an NMOS
1
c
and an NMOS
1
d.
The sources of the NMOSs
1
c
and
1
d
are commonly connected to the drain of an NMOS
1
e
utilized as a constant current source. The source of the NMOS
1
e
is connected to the ground hereafter referred to as the “GND”), and a bias voltage VB
1
is applied to the gate of the NMOS
1
e.
The drain of the NMOS
1
c
is connected to the drain and the gate of a PMOS if, and the source of the PMOS if is connected to a source potential (hereafter referred to as the “VDD”). The drain of the NMOS
1
d
is connected to the drain of a PMOS
1
g
through which the differential output voltage VA is output. The gate of the PMOS
1
g
is connected to the gate of the PMOS
1
f,
with the source of the PMOS
1
g
connected to the VDD.
The level shift stage
2
is provided with an NMOS
2
a
with its gate connected to the drain of the PMOS
1
g
and an NMOS
2
b
utilized as a constant current source to the gate of which a bias voltage VB
2
is applied. The NMOSs
2
a
and
2
b
are connected in series between the VDD and the GND, with the level shift output voltage VB output through the connection point of the NMOSs
2
a
and
2
b.
The output stage
3
is provided with a PMOS
3
a
with its gate connected to the drain of the PMOS
1
g
and an NMOS
3
b
with its gate connected to the drain of the NMOS
2
b.
The PMOS
3
a
and the NMOS
3
b
are connected in series between the VDD and the GND. The drain of the PMOS
3
a
and the drain of the NMOS
3
b
are connected to an output terminal
3
c
through which the output voltage VO is output.
In an operational amplifier structured as described above, the negative phase input voltage VIa input to the negative phase input terminal
1
a
and the positive phase input voltage VIb input through the positive phase input terminal
1
b
cause the NMOSs
1
c
and
1
d
to engage in an on/off operation and the difference between the negative phase input voltage VIa and the positive phase input voltage VIb is amplified to be output as the differential output voltage VA through the drain of the PMOS
1
g.
The differential output voltage VA causes the NMOS
2
a
and the PMOS
3
a
to engage in an on/off operation. The on/off operation of the NMOS
2
a
causes a level shift in the differential output voltage VA, and, as a result, the level shift output voltage VB is output through the source of the NMOS
2
a
to cause the NMOS
3
b
to engage in an on/off operation. This, in turn, causes the amplified output voltage VO to be output through the output terminal
3
c
provided at the drain side of the NMOS
3
b.
However, the operational amplifier in the prior art is yet to address the difficult problems discussed below with respect to power consumption and crossover distortion.
In the circuit structure illustrated in
FIG. 2
, the through current IS flowing from the VDD to the GND at the output stage
3
increases when the VDD is high and when the threshold voltages VT of the PMOS
3
a
and the NMOS
3
b
are low to result in wasteful consumption of power. When the VDD is low and the threshold voltages VT are high on the other hand, the through current IS becomes reduced to 0 to cause crossover distortion.
An example of wasteful consumption of power is now explained. For purposes of simplification, the explanation is given on the assumption that VDD=SV, threshold voltage VTP of PMOS
3
a
=IV and threshold voltage VTN of NMOS
3
b
=IV and that the current Ids between the drain and the source of the PMOS
3
a
is equal to the current Ids between the drain and the source of the NMOS
3
b
when the voltages Vgs between their gates and sources are equal to each other
ILF indicates the current at the level shift stage
2
and VLF indicates the level shift voltage at the level shift stage
2
. Assuming that the voltage Vgs (=VLF=VTN+alpha) between the gate and the source of the NMOS
2
a
required by the NMOS
2
a
to allow the current ILF to flow is approximately 1.2V, the voltage Vgs between the gate and the source of the NMOS
3
b
needs to satisfy Vgs=(VDD−VLF)/2=(5−1.2)/2=1.9V to ensure that the voltage Vgs between the gate and the source of the PMOS
3
a
and the voltage Vgs between the gate and the source of the NMOS
3
b
are equal to each other. Since the NMOS
3
b
constitutes a saturation area, the through current IS that travels through the output stage
3
from the VDD to the GND is calculated as follows through expression (1).
IS
=&mgr;(Vgs at NMOS
3
b
−VTN)
2
=&mgr;(1.9−1)
2
=0.81 &mgr;A  (1)
Next, let us consider a case in which VDD=6V, threshold voltage VTP of PMOS
3
a
=0.6V and threshold voltage VTN of NMOS
3
b
=0.6V. Assuming that alpha hardly changes, VLF is calculated to be approximately 0.8V, i.e., VLF=VTN+alpha=0.8V. The voltage Vgs between the gate and the source of the NMOS
3
b
needs to be Vgs=(6=0.8)/2=2.6V to set the Vgs between the gate and the source of the PMOS
3
a
and the voltage Vgs between the gate and the source of the NMOS
3
b
equal to each other, and in this situation, the through current IS is calculated as in the following expression (2).
IS
=&mgr;(2.6−0.6)
2
=4 &mgr;A  (2)
In other words, under the conditions represented by the expressions (1) and (2), the through current IS at the output stage
3
changes by a factor of 4.94.
When we consider a situation in which VDD=3V, threshold voltage VTP of PMOS
3
a
V, threshold voltage VTN of NMOS
3
b
=IV and the voltage Ids between the drain and the source of the PMOS
3
a
is equal to the voltage Ids between the drain and the source of the NMOS
3
b
when the voltages Vgs between their gates and sources are equal to each other, as an example in which crossover distortion occurs, VLF is calculated to be approximately 1.2V, i.e.,VLF=VTN+alpha=1.2V. The voltage Vgs between the gate and the source of the NMOS
3
b
needs to be Vgs=(VDD−VLF)/2=(3−1.2)/2=0.9V to set the voltage Vgs between the gate and the source of the PMOS
3
a
and the voltage Vgs between the gate and the source of the NMOS
3
b
equal to each other. Since the gate/source voltage Vgs at NMOS
3
b
<VTN in this situation, the through current IS does not flow at the output stage
3
and crossover distortion occurs.
SUMMARY OF TH

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