Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1998-03-11
2001-03-13
Tse, Young T. (Department: 2734)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S316000, C714S743000, C714S744000, C714S795000, C345S215000, C365S230010, C365S230060
Reexamination Certificate
active
06201838
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mobile telephone system, and more particularly, to a mobile communication system having high throughput rate and a mass data process capability.
2. Description of the Related Art
FIG. 1
illustrates a conventional digital video signal processing circuit. The circuit includes an RBA (random block access) controller
30
for controlling an RBA operation mode which enables bit unit (16×16 bits) data access using externally adapted signals /RAS (Row Address Strobe), /CAS (Column Address Strobe), /WE (Write Enable), /DT (Data Transmission), /SC (Serial Clock), /RBA. An address signal generator
10
generates internal address signals using an externally applied start address signal (ROW/COLUMN ADDRESS) in accordance with a control of the RBA controller
30
. A memory cell array
40
stores data in accordance with a control of the RBA controller
30
through the address signal generator
10
. A transmission control unit
20
controls data transmission of the memory cell array
40
in accordance with a control of the RBA controller
30
and the address signal generator
10
. An input/output unit
50
carries out data input/output in accordance with a control of the RBA controller
30
and the transmission control unit
20
.
The address signal generator
10
includes a row address signal generator
11
for generating a row address signal in response to the externally applied start address signal in accordance with a control signal outputted from the RBA controller
30
and a column address signal generator
12
for generating a column address signal. Here, for accessing data in bursts, the start address is applied externally from the CPU, while an address to be accessed at a later time is generated internally.
The transmission control unit
20
includes an RBA selector
21
for outputting a selection signal SELn which serves to store or read data to or from the memory cell array
40
. A serial register
22
converts applied data to a parallel format and outputs the resultant data. An RBA-Y decoder
23
outputs a Y-address signal so as to control the serial register
22
using the column address signal applied thereto in accordance with the control signal outputted from the RBA controller
30
.
The input/output unit
50
includes an input/output block
51
for inputting or outputting data in accordance with the control signal, and an input/output controller
52
for controlling the input/output block
51
in accordance with the control signal outputted from the RBA controller
30
.
FIG. 2
illustrates a detailed block diagram of the RBA controller
30
in the circuit of FIG.
1
. The controller
30
includes a mode selector
34
for determining whether to operate under a present operation mode or a new mode with regard to a semiconductor chip operation mode, by checking an externally applied control signal. An X-state pointer
31
(0‥7 rows) counts a displacement value of a “row address” signal currently being accessed in a way in which the displacement value is increased by one per cycle of an externally applied serial clock SCx in accordance with a selection of the mode selector
34
. A Y-state pointer
32
(0-31 column) counts a displacement value of a column address signal currently being accessed in a way in which the displacement value is increased by one per cycle of the externally applied serial clock SCx in accordance with a selection of the mode selector
34
. An internal control signal generator
33
receives the counted value of the X-state and Y-state pointers
31
,
32
and externally applies signals /RAS, /CAS, and generates internal control signals /RASi, /CASi, transmission signal (XF), register enable signal (RGE), serial decoder enable signal (SDE) so as to control respective portions in a semiconductor chip. An internal clock signal generator
35
generates an internally required system clock signal SYCK in accordance with the externally applied serial clock signal SCx.
The conventional digital video processing circuit will now be described in more detail.
For the purpose of performing data compression and restoration in such a digital video signal processing circuit, there is prescribed a basic 16×16 bits of data processing block size for carrying out a block unit random read and a block unit serial write. The block size of 16×16 bits serves to carry out a successive data read/write operation.
Beginning with an externally applied start address signal ROW/COLUMN ADDRESS, the address signal generation unit
10
generates an address signal which is to be accessed for data processing. At this time, the X-state pointer
31
in the RBA controller
30
continues counting from zero to fifteen a displacement value of a row address signal presently being accessed thereto following a start row address signal where an externally applied serial clock signal SCx is increased by one every 16 cycles. The Y-state pointer
32
in the RBA controller
30
continues counting from zero to fifteen a displacement value of a column address signal presently being accessed thereto following a start column address signal where an externally applied serial clock signal SCx is increased by one per cycle.
The counted output values XRn, YRn, of the X-state and Y-state pointers
31
,
32
are respectively applied to the internal control signal generator
33
and to the mode selector
34
.
Then, the internal control signal generator
33
receives the output values XRn, YRn from the respective X-state and Y-state pointers
31
,
32
, an externally applied row address strobe signal /RASx, and an externally applied column address strobe signal /CASx. The internal control signal generator
33
generates an internal row address strobe signal /RASi, an internal column address strobe signal /CASi, a transmission signal XF, a register enable signal RGE, and a serial decoder enable signal SDE so as to respectively control portions in the address signal generator
10
and the transmission control unit
20
.
The mode selector
34
serves to determine whether a semiconductor chip operation mode is to follow a present mode or a new mode by checking an externally applied control signal for every 16×16 bits (256 cycles) with regard to the externally applied serial clock signal SCx. In the serial block write mode of the RBA mode, data is written in units of 16×16 blocks. Thus, if the initial start write address is given as (0,0) when the first block is written, the start address of the second block is given as an address value that is a multiple of 16 which does not overlap with that of the first block. For example, (16,0) is given to the second block. Thus, an address that is 16 greater than the address of the previous block is given to a new block that is to be written.
Likewise, the address signal generator
11
which receives an internal row address strobe signal /RASi from the internal control signal generator
33
in the RBA controller
30
, generates an internal row address signal to the memory cell array
40
using the start row address signal ROW ADDRESS. The column address signal generator
12
outputs an internal column address to the RBA selector
21
and the RBA-Y decoder
23
, respectively, in the transmission control unit
20
, using the control signal outputted from the RBA controller
30
and an externally applied start column address signal COLUMN ADDRESS.
At this time, RBA-Y decoder
23
receives the decoder enable signal SDE outputted from the RBA controller
30
, and the column address signal outputted from the column address generator
12
, and outputs the received signals to the RBA selector
21
and the serial register
22
, whereby the RBA selector
21
outputs a Y-address signal outputted from the RBA-Y decoder
23
.
Accordingly, the memory cell array
40
receives a row address signal from the row address generator
11
, and a column address signal from the RBA selector
21
. When the RBA selector
21
outputs a selection signal SELn for writing data in the memory c
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Tse Young T.
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