Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
1994-04-13
2001-01-30
Cuchlinski, Jr., William A. (Department: 3661)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C324S076110
Reexamination Certificate
active
06182020
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to tools for computer-aided software engineering. More specifically, the present invention relates to a software-implemented tool for assisting in the design of logic circuits having interconnected circuit elements, the invention providing a technique for checking a user's design against a set of design rules.
Computer design tools are known for assisting circuit designers in the laying out and simulation testing of logic circuitry. One such software base system is that system sold under the trademark MAX-PLUS available from Altera Corporation of San Jose, Calif. Typically, the designer uses such a system to initially design and subsequently test the operation of the design using computer simulation techniques. With reference to
FIG. 1
, a typical computer logic simulation technique proceeds by initially providing a logic design in the form of a schematic or netlist stored in a file
10
and converting the netlist by means of a logic compiler
12
into a simulator logic netlist
14
that is used by a logic simulator
15
. In use, a set of simulation input vectors
16
is also provided to the logic simulator, which reads the simulator logic netlist, along with the simulator input vectors and “simulates” the operation of the logic design by propagating logic levels through the logic primitives in order to generate a set of output vectors
18
, which are the simulated outputs of the logic design. This process has been found to be exceedingly useful in the field of logic design, particularly for complex circuits intended for physical implementation in erasable programmable logic devices (EPLDs) and mask programmable logic devices (MPLDs). Recently, with volume applications of circuits, the trend has been to either initially design the logic circuitry with MPLD implementation in mind, or to convert an original design intended for implementation in EPLD form to a functionally identical design intended for implementation in an MPLD form. Typically, a given user's design must conform to a set of design rules governing permitted and prohibited structural and functional configurations, in order for the design to be useful and reliable. Failure to comply with one or a few of the design rules, while not necessarily fatal to the operation of a circuit, can introduce operational uncertainties under special conditions, sometimes with a cumulative effect leading to a partially inoperative or, in extreme cases, a totally inoperative circuit design. While the logic simulation process is intended to reveal erroneous or inconsistent responses to stimulation by the test input vectors, such a result is only obtained after an often lengthy and time consuming simulation of the original design.
SUMMARY OF THE INVENTION
The invention provides a technique for checking a user's initial design against a predetermined set of design rules in order to uncover potential problems with an original design, which could result in an unreliable circuit, whether implemented in EPLD or MPLD form.
In its broadest aspect, the invention comprises a method for verifying an initial logic design in a computer-aided logic design system for designing and testing logic circuitry prior to physical implementation. The method includes the steps of providing a set of design rules expressing permitted and prohibited structural and functional logic device relationships, providing a logic design file incorporating the initial logic design in computer-readable form, comparing at least portions of the initial logic design with at least some of the design rules in the set, and providing a user-discernible indication of any violation of the design rules by the initial logic design. The method includes the step of enabling a user to select the level of design rule compliance from among a hierarchy of such levels. In addition, the method includes the step of providing a user-selectable list of optional rule selections. Thus, all rules in the set or only selected ones of the rules in the set are used to check the initial logic design for design rule compliance, with the level of compliance also being selectable by the user.
Both the hierarchy of levels of design rule compliance and the user-selectable list of optional rule selections are preferably visibly displayed to the user to aid in the selection of choices.
The method also provides for an additional comparison of at least some of the design rules with a synthesized version of the initial logic design in those cases in which the initial design undergoes logic synthesis. This capability is provided in order to check for design rule violations potentially introduced by the process of logic synthesis.
The invention provides a convenient and effective technique for verifying the compliance of an initial logic design against the set of design rules applicable to the type of programmable device in which the design will be implemented. Thus, the invention can be used in conjunction with ELPD and MLPD implementations. In addition, the invention can be readily expanded to include changes to an existing set of design rules or to implement new design rules found necessary or desirable in the computer-aided logic design process.
For a fuller understanding of the nature and advantages of the invention, reference should be had to the ensuing detailed description, taken in conjunction with the accompanying drawings.
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Altera Corporation
Cuchlinski Jr. William A.
Townsend and Townsend / and Crew LLP
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