Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
1998-09-15
2001-08-14
Ellis, Richard L. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
C712S219000
Reexamination Certificate
active
06275924
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to processors and more particularly to a method and system for buffering instructions in a processor.
BACKGROUND OF THE INVENTION
Many modern processors utilize a pipeline within the processor for greater efficiency. With the use of a pipeline, a task is subdivided into a number of sequential subtasks. The division of a task into sequential subtasks allows fetching, decoding, and execution of a number of program instructions at any given time. Therefore, at any particular time, several instructions may be processed in various stages at the pipeline. Many such processors include a pipeline having a decode stage. At the decode stage of a pipeline, an instruction obtained from program memory is decoded so that the instruction may be executed. After an instruction is decoded, it is not necessary to store the instruction within the processor. However, until the instruction is decoded, the instruction obtained from program memory must be stored. In order to store the instruction until it has been decoded, many processors utilize an instruction buffer.
Conventionally, an instruction buffer includes enough registers to store a number of instructions equal to the number of stages up to and including the decode stage. For example, if a pipeline has a prefetch, a fetch, and a decode stage as its first three stages, the associated instruction buffer would have three registers for storing three instructions. This number of registers in an instruction buffer has been conventionally used because it allows retention of instructions that are being obtained when it is determined that the decode stage is stalled.
Although the use of an instruction buffer allows resuming of processing without loss of information, it is not without its disadvantages. For example, as the size of common instruction fetches increases, each register within the instruction buffer grows in size, which requires additional silicon area.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an improved method and system for buffering instructions in a processor. The present invention provides a system and method for buffering instructions in a processor that addresses shortcomings of prior systems and methods.
According to one embodiment of the invention, a method of buffering instructions in a processor having a pipeline having a decode stage includes detecting stalling of the decode stage, reissuing a previous fetch for an instruction in a memory until the decode stage is no longer stalled, and writing the fetch instruction into an instruction buffer after the decode stage is no longer stalled.
According to another embodiment of the invention, a processor pipeline includes a plurality of sequential stages followed by a decode stage and a limited instruction buffer operable to concurrently store a number of instructions less than or equal to the number of sequential stages, and no more. The processor pipeline also includes a counter system. The counter system includes a counter for storing a count designating an address of a memory location that stores an instruction for receipt by the limited instruction buffer. The counter system is also operable to adjust the count of the counter based on a status of the decode stage. The plurality of sequential stages includes a fetch stage that is operable to fetch the instruction at the address designated by the count.
Embodiments of the invention provide numerous technical advantages. For example, in one embodiment of the invention, a limited instruction buffer may be used rather than a conventional larger instruction buffer for buffering instructions fetched from a program memory. The smaller size of the limited instruction buffer reduces silicon area, allowing for smaller devices or the use of such silicon area in other areas of the processor.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
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Mital Deepak
Subash Chandar G.
Ellis Richard L.
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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