Smart erase algorithm with secure scheme for flash EPROMs

Details Smart erase algorithm with secure scheme for flash EPROMs Smart erase algorithm with secure scheme for flash EPROMs

1993-01-05

1996-02-13

Swann, Tod R.

Boots, shoes, and leggings

3642446, 3642467, 3642493, 3649543, 36496576, 36496579, 364969, 364DIG1, 364DIG2, 365218, G06F 1216

Patent

active

054918090

ABSTRACT:
A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of an erased state or a state secured from erasure or at a second level for each block not so detected; then selecting for erasure blocks that have their respective flags set at the second level; and then erasing the selected blocks.

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"A Single Transistor EEPROM Cell and its Implementation in a 512K CMOS EEPROM", S. Mukherjee et al, IEDM 1985, pp. 616-619.
"A 9ons 100K Erase/Program Cycle Megabit Flash Memory", V. Kynett et al, ISSCC 1989, pp. 140-141.

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