Electric power conversion systems – Current conversion – Using semiconductor-type converter
Reexamination Certificate
2000-08-17
2001-09-11
Wong, Peter S. (Department: 2838)
Electric power conversion systems
Current conversion
Using semiconductor-type converter
C363S137000, C363S098000
Reexamination Certificate
active
06288921
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority to Japanese Patent Application No. 11-247133 filed Sep. 1, 1999, the entire content of which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a control apparatus for a power converter, each phase of the power converter may output three levels of voltages, and more specifically to a control apparatus that may minimize a switching loss of a semiconductor switching device at a time of switching by minimizing the number of turning ON/OFF (switching) of the semiconductor switching device and may control a waveform of output voltage suitably.
2. Description of the Background
FIG. 1
is a circuit diagram showing a main circuit of a power converter that may output three levels of voltages and a conventional control apparatus for the power converter.
In
FIG. 1
, a converter
1
includes two DC (Direct Current) capacitors
2
and
3
, twelve semiconductor switching devices S
11
, S
12
, S
13
, S
14
, S
21
, S
22
, S
23
, S
24
, S
31
, S
32
, S
33
and S
34
, and diodes. A DC power source
4
is connected to the converter
1
. A controller for the converter
1
includes a command voltage generator
5
, a carrier wave generator
6
, six comparators
7
,
8
,
9
,
10
,
11
and
12
, and six inverters
13
,
14
,
15
,
16
,
17
and
18
. G
11
-G
14
, G
21
-G
24
and G
31
-G
34
represent gate signals for the semiconductor switching devices S
11
-S
14
, S
21
-S
24
and S
31
-S
34
respectively.
FIG. 2
is one example of a waveform that indicates an operation of the controller for the converter
1
in FIG.
1
. The operation of each portion of the controller is described referring to FIG.
2
.
The command voltage generator
5
generates output voltage commands VU*, VV* and VW* to be output from the converter
1
on the basis of a power or a current flowing in a load connected to AC (Alternating Current) terminals of the converter
1
. The carrier wave generator
6
generates two carrier waves VCP and VCN in order to modulate the output voltage commands VU*, VV* and VW*. The carrier wave VCP has the same triangular waveform as the carrier wave VCN. The carrier wave VCP sets the minimum value at 0 (zero), while the carrier wave VCN sets the maximum value at 0 (zero) . The comparator
7
compares the output voltage command VU* with the carrier wave VCP, and outputs “1” as the gate signal G
11
of the semiconductor switching device S
11
and “0” as the gate signal G
13
of the semiconductor switching device S
13
at the time that the output voltage command VU* is higher than the carrier wave VCP. On the contrary, where the output voltage command VU* is lower than the carrier wave VCP, the gate signal G
11
is made “0” and the gate signal G
13
is made “1”. A gate signal “1” represents a command for turning on the corresponding semiconductor switching device, while a gate signal “0” represents a command for turning off the corresponding semiconductor switching device. The inverter
13
inverts a logic of the gate signal G
11
and G
13
.
Likewise, the comparator
8
and the inverter
14
determine the gate signals G
12
and G
14
of the semiconductor switching devices S
12
and S
14
on the basis of the output voltage commands VU* and the carrier wave VCN.
Description of the operation of the other comparators and inverters in
FIG. 1
are omitted, because the other comparators and inverters operate in the same way as the comparators
7
and
8
, and the inverters
13
and
14
.
The corresponding semiconductor switching devices S
11
-S
34
turn on and off in response to the above determined gate signals G
11
-G
34
, thereby converting a DC voltage supplied from the DC power source
4
into output voltages based on the output voltage commands VU*, VV* and VW*. The DC capacitors
2
and
3
are used for smoothing and stabilizing an electric power supplied from the DC power source
4
.
As described above, the semiconductor switching devices S
11
-S
34
repeatedly turn on and off at a frequency based on the frequency of the carrier waves VCP and VCN, when the converter
1
generates a suitable voltage. As switching frequency of the semiconductor switching device rises, a switching loss caused by turning on and off the semiconductor switching device increases. As a result, power efficiency of the converter
1
lowers and a converting rate of voltage, that is called “utilization factor”, is also reduced due to an increase of unnecessary switching.
Imbalance of switching losses among the semiconductor switching devices S
11
-S
34
may occur depending on conditions of an output voltage or an output current of the converter
1
, thereby raising a temperature of the only one part of the semiconductor switching devices due to heat loss, and giving rise to a thermal stress. With the advance of the thermal stress, the semiconductor switching devices may break.
In case that a current flows into the DC capacitor through the only semiconductor switching devices S
12
, S
22
, S
32
, S
13
, S
23
and S
33
and diodes which are directly connected to the AC terminals of the converter
1
, that is, at least one phase of the converter
1
has the same potential as a joint of the DC capacitors
2
and
3
has, directions of currents flowing into the DC capacitors
2
and
3
are different from each other, whereby voltage imbalance between the DC capacitors
2
and
3
may occur. With the advance of the voltage imbalance, an output voltage of the converter
1
may not be controlled suitably, or the main circuit may break because of the excessive increase of voltages of either DC capacitor
2
or
3
.
SUMMARY OF THE INVENTION
Accordingly, one object of this invention is to provide a control apparatus for a power converter which may minimize the number of switching of semiconductor switching devices.
Another object of this invention is to provide a control apparatus for a power converter which may balance temperatures of semiconductor switching devices.
Another object of this invention is to provide a control apparatus for a power converter which may balance voltages of the positive side of capacitor and the negative side of capacitor and may control an output voltage of the converter suitably.
The present invention provides a control apparatus for a power converter having a plurality of semiconductor switching devices that converts DC power into AC power and outputs three levels of voltages, including a command voltage generator configured to output a command voltage vector that represents a voltage to be output from the power converter, an integrator configured to calculate a difference integral vector by integrating a difference between the command voltage vector and an output voltage vector that represents a voltage command for the power converter, a difference vector calculator configured to calculate difference vectors by subtracting the command voltage vector from each of the possible output voltage vectors, a vector selector configured to select one of the possible output voltage vectors which corresponds to one of the difference vectors making the largest angle with the difference integral vector as the output voltage vector only if the difference integral vector exceeds a predetermined value, and a gate signal generator configured to determine one of switching states that includes a plurality of ON-OFF pattern signals for turning on and off the semiconductor switching devices on the basis of the output voltage vector.
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patent: 4052657 (1977-10-01), Kleiner et al.
patent: 4545002 (1985-10-01), Walker
patent: 4942511 (1990-07-01), Lipo et al.
patent: 5450306 (1995-09-01), Garces et al.
patent: 5621628 (1997-04-01), Miyazaki et al.
patent: 5852558 (1998-12-01), Julian et al.
patent: 6031738 (2000-02-01), Lipo et al.
Kanai Takeo
Kusunoki Kiyoshi
Morikawa Ryuichi
Nishikawa Tadashi
Uchino Hiroshi
Foley & Lardner
Kabushiki Kaisha Toshiba
Vu Bao Q.
Wong Peter S.
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