Static information storage and retrieval – Floating gate – Particular biasing
Utility Patent
1999-05-24
2001-01-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185280
Utility Patent
active
06169690
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device and its data programming method.
BACKGROUND OF THE INVENTION
A memory cell of an NAND type EEPROM is shown in FIG.
28
.
FIG. 28
is a schematic sectional view of the memory cell MC. The gate insulation film GO which is formed between floating gate FG and channel region CA is sufficiently thin to allow an electron tunnel effect to occur between the floating gate FG and the channel region CA. Electrons are emitted from the floating gate FG to the channel region CA by supplying a high voltage to the substrate Sb, and 0V to the control gate CG, so that one of a binary data is stored in the memory cell. On the other hand, when the other of a binary data is stored in the memory cell, electrons are injected from the channel region CA to the floating gate FG. In order to inject electrons to the floating gate FG, a high voltage is supplied to the control gate CG, and 0V is supplied to the channel region CA, source S and drain D. A part of a memory cell array of the NAND type EEPROM is shown in FIG.
29
(
a
). The memory cells MC are serially connected between the select transistor ST and the transistor
10
. Further, FIG.
29
(
b
) shows voltage waveform diagrams at the respective nodes shown in FIG.
29
(
a
). When data are programmed to the memory cells MC, first electrons are emitted from the floating gates FG of all the memory cells MC to the substrate by setting all the row lines WL
1
to WLn connected to the control gates CG to 0 V and the substrate to a high voltage. After that, a high voltage is supplied to the row select line S connected to the gates of the select transistors ST connected to the memory cells MC to which data are to be written. At the same time, signal &phgr; which is applied to the gates of the transistors
10
is set to 0 V to turn off transistors
10
to disconnect the memory cells MC from the reference potential VSS. When electrons are injected to the floating gates FG of the memory cells MC, the row line WL corresponding thereto is set to the high potential V
1
, and column lines D corresponding thereto are set to 0 V. At this time, a potential difference between the floating gates FG and the channel region CA becomes large enough to occur the electron tunnel effect, so electrons are injected to the floating gates FG from the channel region CA. On the other hand, the non-selected row lines WL are set to the potential V
2
lower than the high potential V
1
. At this time, although the potential of the column lines D is 0 V, since the potential V
2
is low, the potential difference between the floating gates FG of the memory cells applied the potential V
2
and the channel region CA is not large enough to cause the electron tunnel effect, so electrons are not injected to the floating gates FG of the memory cells applied the potential V
2
. In the memory cells connected to the row line WL of the high potential V
1
, if the column lines D are set to the potential V
3
, since the potential difference between the floating gates FG and the channel region CA is not large enough to cause the electron tunnel effect, electrons are not injected to the floating gates FG. In FIG.
29
(
b
), at time T
1
, electrons are injected to the floating gate FG of memory cell
2
n, but not injected into the floating gate FG of the memory cell
1
n because the voltage of the column line D
1
is the potential V
3
. In the same way, at time T
2
, electrons are injected to the floating gate FG of memory cell
11
, but not injected to the floating gate FG of the memory cell
21
.
In the memory cells MC, if the electrons are injected to the floating gate FG thereof, the threshold voltage thereof becomes a positive value; and if the electrons are emitted from the floating gate FG thereof, the threshold voltage thereof becomes a negative value. In a data read mode, when the memory cell MC is selected, the gate thereof is set to a logic “0”, for instance to 0 V. When the threshold voltage of the selected memory cell MC is the negative value, the selected memory cell MC is turned on. However, when the threshold voltage of the selected memory cell MC is the positive value, the selected memory cell MC is turned off. The data stored in the selected memory cell MC is detected depending on whether or not the selected memory cell MC is turned on. On the other hand, the gate of the non-selected memory cell MC connected to the selected memory cell is set to a logic “1”, for instance to 5 V. So the non-selected memory cell MC is turned on even when electrons are injected into the floating gate.
Referring to
FIG. 30
, the data reading operation will be explained. The depletion type MOS transistor L
1
which acts as a load for the memory cell, the select transistor (enhancement type) ST, the memory cells M
1
to M
8
, and the transistor
10
are connected in series between the power supply voltage VDD and the reference potential (VSS). The gate of the transistor L
1
is connected to a connecting point (node N
1
) between the transistor L
1
and the select transistor ST. The signal X for selecting memory block
11
composed of the memory cells M
1
to M
8
is supplied to the gate of the select transistor ST. Further, the signals W
1
to W
8
for selecting one of the memory cell of the memory block
11
are supplied to the gates of the memory cells M
1
to M
8
, respectively. The sense amplifier
12
is connected to the node N
1
. The data stored in the selected memory cell can be read by being detected the voltage level of the node N
1
by the sense amplifier
12
. In the data read mode, the signal &phgr; which is applied to the gate of the transistor
10
is a logic “1”. So the transistor
10
is turned on. The memory block
11
is connected to the reference potential through the transistor
10
in the data read mode. In the circuit shown in
FIG. 30
, the assumption is made that electrons are emitted from the floating gates of the memory cells M
2
and M
4
, so the threshold voltages of the memory cells M
2
and M
4
are negative, and further the memory cell transistor M
4
is selected, for instance. The threshold voltages of the other memory cells M
1
, M
3
, and M
5
to M
8
are positive. In this case, as shown by a timing chart in
FIG. 31
, the signal X is set to a logic “1”, the signals W
1
to W
3
, W
5
to W
8
are set to a logic “1”, and the signal W
4
is set to a logic “0”. By the above-mentioned setting, the select transistor ST and the memory cells M
1
to M
3
and M
5
to M
8
are turned on. Further, since the threshold voltage of the memory cell M
4
is negative, this memory cell M
4
is also turned on. Accordingly, the node N
1
is discharged toward the reference potential through the select transistor ST, the memory cells M
1
to M
8
, and the transistor
10
. The data stored in the memory cell M
4
can be read by being detected the voltage of the node N
1
by the sense amplifier
12
. After that, the memory cell M
3
is assumed to be selected. In this case, the signal W
3
is set to a logic “0”, and all other signals are set to a logic “1”. In this case, since the threshold voltage of the memory cell M
3
is positive, the memory cell M
3
is turned off. Thus, since the discharging path of the node N
1
toward the reference potential is cut off, this node N
1
is charged toward the power source voltage VDD through the transistor L
1
. By detecting the charged voltage of the node N
1
, the data can be read from the memory cell M
3
.
However, in the case where data of a logic “1” or a logic “0” is stored in the memory cell depending on whether the threshold voltage of the memory cell is negative or positive, the amount of current flowing through the memory block is according to the number of the memory cells having positive threshold voltages and the number of the memory cells having negative threshold voltages which are included in the memory block. So the amount of current flowing through each of the memory blocks is different from each other. Thus, the discharging speed at the node
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Le Vu A.
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