High performance flip chip package

Details High performance flip chip package High performance flip chip package

2000-03-09

2001-09-25

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S015000

Reexamination Certificate

active

06294403

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor packaging and in particular to an apparatus and method of manufacture for a high performance flip chip package for semiconductor devices.
While silicon process technology has advanced significantly in the past decade, for the most part, the same decades-old package technology continues as the primary packaging means. Epoxy or solder die attach along with aluminum or gold wire bonding to lead frame is still the preferred semiconductor package methodology. Advances in semiconductor processing technology, however, have made the parasitics associated with conventional packages more of a performance limiting factor. This is particularly true in the case of power switching devices where, as in the case of power MOSFETs, the on-resistance of these devices continues to push the lower limits. Thus, the parasitic resistance introduced by the bond wires and the lead frame in conventional packages becomes much more significant for such high current devices as power MOSFETs. Furthermore, the continuous shrinking of geometries and the resulting increase in chip densities has given rise to an increasing demand for semiconductor packages with lead counts higher than that offered by the conventional packaging techniques.
Ball grid array and flip chip technologies were developed to address some of these demands. Both of these packaging technologies provide for a more direct connection between the silicon die and the printed circuit board as well as providing for higher interconnect densities. There is always room for improvement however. For example, a typical ball grid array package consists of a BT resin laminated board which serves as an interposer layer between the silicon die and the printed circuit board (PCB). Because of poor heat dissipation from the laminated board, external heat sinks and additional PCB copper layers are often required to dissipate excess heat.
FIELD OF THE INVENTION
In the case of conventional flip chip technology, among other shortcomings, heat dissipation is essentially governed by the die size and connection to the back side of the die is not easily facilitated (often requiring a bond wire connection). These limitations (poor heat dissipation and resistive contact to back side) become quite significant in high current applications such as power switching devices. A substantial improvement in the performance of flip chip packages is offered by Bencuya et al. in commonly assigned provisional Patent Application No. 60/088,651, entitled “Low Resistance Package for Semiconductor Devices.” In one embodiment, this improved package eliminates wire bonding by making direct connection between an array of solder balls on one conductive surface of the die and a lead frame element, while connection to the opposite side is made by a die attached mechanism. This package exhibits significantly lower resistance; however, it still relies on a lead frame which adds residual resistance to the current path, and is not the smallest package possible for a given die size.
There is therefore a need for a high density semiconductor package whose attributes are minimal parasitic resistance and good heat dissipation, and that is readily manufacturable.
SUMMARY OF THE INVENTION
The present invention provides an improved semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Broadly, according to the present invention, a silicon die is attached to a carrier (or substrate) that has a cavity substantially surrounding the die. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of the die as well as the edges of the carrier surrounding the die. In one embodiment, the outer array of solder balls connects to a conductive carrier and provides for a low resistance connection to the back side of the die. In applications where no connection to the back side of the die is required, the carrier and the array of solder balls connecting to it may act as a thermal via for dissipating heat. Alternatively, the carrier may be of dielectric material with selective conductive traces to make selective contact to traces on the board through the outer array of solder balls. The package of the present invention also reduces the number of steps required in the assembly process flow and is manufactured using standard materials and equipment. The resulting package not only exhibits minimal resistance and improved heat dissipation, it is very thin and light as well as being cost-effective to manufacture.
Accordingly, in one embodiment, the present invention provides a semiconductor package including a carrier having a cavity sized for housing a silicon die, a silicon die having a first surface attached to the inside of the cavity, the silicon die having a thickness substantially equal to a depth of the cavity such that a second surface of the silicon die and a surface of the edges of the carrier surrounding the silicon die form a substantially uniform plane, and an array of solder balls distributed across the uniform plane connecting to the second surface of the silicon die as well as the surface of the edges of the carrier surrounding the silicon die.
In another embodiment, the present invention provides a method of packaging a silicon die including the steps of: stamping a cavity in a carrier for housing the silicon die; attaching a first surface of the silicon die inside the cavity such that a second surface of the silicon die and a surface of the edges of the carrier surrounding the silicon die form a substantially uniform plane; and disposing an array of solder balls across the substantially uniform plane with an outer array connecting to the carrier and an inner array connecting to the second surface of the silicon die.
A better understanding of the nature and advantages of the improved flip chip package of the present invention may be gained with reference to the detailed description and drawings below.


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